IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Also new SecCore module created for FspMultiPhaseSiInit API New ARCH_UPD introduced for enhancing FSP debug message flexibility now bootloader can pass its own debug handler function pointer and FSP will call the function to handle debug message. To support calling bootloader functions, a FspGlobalData field added to indicate if FSP needs to switch stack when FSP running on separate stack from bootloader. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu
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mergify[bot]
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52
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
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52
IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
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## @file
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# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.
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#
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# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = Fsp22SecCoreS
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FILE_GUID = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32
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#
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[Sources]
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SecFspApiChk.c
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SecFsp.h
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[Sources.IA32]
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Ia32/Stack.nasm
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Ia32/Fsp22ApiEntryS.nasm
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Ia32/FspApiEntryCommon.nasm
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Ia32/FspHelper.nasm
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[Binaries.Ia32]
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RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
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[Packages]
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MdePkg/MdePkg.dec
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IntelFsp2Pkg/IntelFsp2Pkg.dec
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[LibraryClasses]
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BaseMemoryLib
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DebugLib
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BaseLib
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PciCf8Lib
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SerialPortLib
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FspSwitchStackLib
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FspCommonLib
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FspSecPlatformLib
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[Ppis]
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gEfiTemporaryRamSupportPpiGuid ## PRODUCES
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99
IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm
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IntelFsp2Pkg/FspSecCore/Ia32/Fsp22ApiEntryS.nasm
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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SECTION .text
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;
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; Following functions will be provided in C
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;
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extern ASM_PFX(FspApiCommon)
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extern ASM_PFX(FspMultiPhaseSiInitApiHandler)
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;----------------------------------------------------------------------------
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; NotifyPhase API
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;
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; This FSP API will notify the FSP about the different phases in the boot
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; process
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(NotifyPhaseApi)
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ASM_PFX(NotifyPhaseApi):
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mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspSiliconInit API
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;
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; This FSP API initializes the CPU and the chipset including the IO
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; controllers in the chipset to enable normal operation of these devices.
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspSiliconInitApi)
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ASM_PFX(FspSiliconInitApi):
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mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspMultiPhaseSiInitApi API
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;
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; This FSP API provides multi-phase silicon initialization, which brings greater
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; modularity beyond the existing FspSiliconInit() API.
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; Increased modularity is achieved by adding an extra API to FSP-S.
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; This allows the bootloader to add board specific initialization steps throughout
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; the SiliconInit flow as needed.
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspMultiPhaseSiInitApi)
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ASM_PFX(FspMultiPhaseSiInitApi):
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mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspApiCommonContinue API
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;
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; This is the FSP API common entry point to resume the FSP execution
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspApiCommonContinue)
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ASM_PFX(FspApiCommonContinue):
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;
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; Handle FspMultiPhaseSiInitApiIndex API
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;
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cmp eax, 6
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jnz NotMultiPhaseSiInitApi
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pushad
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push DWORD [esp + (4 * 8 + 4)] ; push ApiParam
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push eax ; push ApiIdx
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call ASM_PFX(FspMultiPhaseSiInitApiHandler)
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add esp, 8
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mov dword [esp + (4 * 7)], eax
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popad
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ret
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NotMultiPhaseSiInitApi:
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jmp $
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ret
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;----------------------------------------------------------------------------
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; TempRamInit API
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;
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; Empty function for WHOLEARCHIVE build option
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(TempRamInitApi)
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ASM_PFX(TempRamInitApi):
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jmp $
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ret
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;----------------------------------------------------------------------------
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; Module Entrypoint API
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;----------------------------------------------------------------------------
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global ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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jmp $
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@@ -1,7 +1,7 @@
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;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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@@ -62,6 +62,9 @@ FspApiCommon2:
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cmp eax, 3 ; FspMemoryInit API
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jz FspApiCommon3
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cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API
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jz FspApiCommon3
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call ASM_PFX(AsmGetFspInfoHeader)
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jmp ASM_PFX(Loader2PeiSwitchStack)
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@@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -160,6 +160,16 @@ FspGlobalDataInit (
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SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr);
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SetFspSiliconInitUpdDataPointer (NULL);
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//
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// Initialize OnSeparateStack value.
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//
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if (PcdGet8 (PcdFspHeapSizePercentage) != 0) {
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//
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// FSP is running on its own stack and may need switching stack when calling bootloader functions.
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//
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GetFspGlobalDataPointer ()->OnSeparateStack = 1;
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}
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//
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// Initialize serial port
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// It might have been done in ProcessLibraryConstructorList(), however,
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@@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -59,7 +59,7 @@ FspApiCallingCheck (
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Status = EFI_UNSUPPORTED;
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}
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}
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} else if (ApiIdx == FspSiliconInitApiIndex) {
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} else if ((ApiIdx == FspSiliconInitApiIndex) || (ApiIdx == FspMultiPhaseSiInitApiIndex)) {
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//
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// FspSiliconInit check
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//
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@@ -68,7 +68,7 @@ FspApiCallingCheck (
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} else {
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if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) {
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Status = EFI_UNSUPPORTED;
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} else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {
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} else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, ApiParam))) {
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Status = EFI_INVALID_PARAMETER;
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}
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}
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@@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@@ -221,6 +221,12 @@ SecTemporaryRamSupport (
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UINTN CurrentStack;
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UINTN FspStackBase;
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//
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// Override OnSeparateStack to 1 because this function will switch stack to permanent memory
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// which makes FSP running on different stack from bootloader temporary ram stack.
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//
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GetFspGlobalDataPointer ()->OnSeparateStack = 1;
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if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {
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CurrentStack = AsmReadEsp();
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