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IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698

To enhance FSP silicon initialization flexibility an optional
Multi-Phase API is introduced and FSP header needs update for
new API offset. Also new SecCore module created for
FspMultiPhaseSiInit API

New ARCH_UPD introduced for enhancing FSP debug message
flexibility now bootloader can pass its own debug handler
function pointer and FSP will call the function to handle
debug message.
To support calling bootloader functions, a FspGlobalData field
added to indicate if FSP needs to switch stack when FSP running
on separate stack from bootloader.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu
2020-04-30 09:28:35 +08:00
committed by mergify[bot]
parent ceacd9e992
commit f2cdb268ef
11 changed files with 352 additions and 16 deletions
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11
IntelFsp2Pkg/Include/FspGlobalData.h
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@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -22,6 +22,7 @@ typedef enum {
FspMemoryInitApiIndex,
TempRamExitApiIndex,
FspSiliconInitApiIndex,
FspMultiPhaseSiInitApiIndex,
FspApiIndexMax
} FSP_API_INDEX;
@@ -52,10 +53,14 @@ typedef struct {
VOID *SiliconInitUpdPtr;
UINT8 ApiIdx;
UINT8 FspMode; // 0: FSP in API mode; 1: FSP in DISPATCH mode
UINT8 Reserved3[30];
UINT8 OnSeparateStack;
UINT8 Reserved3;
UINT32 NumberOfPhases;
UINT32 PhasesExecuted;
UINT8 Reserved4[20];
UINT32 PerfSig;
UINT16 PerfLen;
UINT16 Reserved4;
UINT16 Reserved5;
UINT32 PerfIdx;
UINT64 PerfData[32];
} FSP_GLOBAL_DATA;