MdeModulePkg/Ata/AtaAtapiPassThru: Enable/disable DEVSLP per policy
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Ruiyu Ni
parent
06766c0e19
commit
f3100a1a2f
@ -2218,6 +2218,213 @@ Error6:
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return Status;
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return Status;
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}
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}
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/**
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Read logs from SATA device.
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@param PciIo The PCI IO protocol instance.
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@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
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@param Port The number of port.
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@param PortMultiplier The multiplier of port.
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@param Buffer The data buffer to store SATA logs.
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@param LogNumber The address of the log.
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@param PageNumber The page number of the log.
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@retval EFI_INVALID_PARAMETER PciIo, AhciRegisters or Buffer is NULL.
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@retval others Return status of AhciPioTransfer().
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**/
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EFI_STATUS
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AhciReadLogExt (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_AHCI_REGISTERS *AhciRegisters,
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IN UINT8 Port,
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IN UINT8 PortMultiplier,
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IN OUT UINT8 *Buffer,
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IN UINT8 LogNumber,
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IN UINT8 PageNumber
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)
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{
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EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
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EFI_ATA_STATUS_BLOCK AtaStatusBlock;
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if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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///
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/// Read log from device
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///
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ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
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ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
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ZeroMem (Buffer, 512);
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AtaCommandBlock.AtaCommand = ATA_CMD_READ_LOG_EXT;
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AtaCommandBlock.AtaSectorCount = 1;
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AtaCommandBlock.AtaSectorNumber = LogNumber;
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AtaCommandBlock.AtaCylinderLow = PageNumber;
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return AhciPioTransfer (
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PciIo,
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AhciRegisters,
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Port,
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PortMultiplier,
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NULL,
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0,
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TRUE,
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&AtaCommandBlock,
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&AtaStatusBlock,
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Buffer,
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512,
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ATA_ATAPI_TIMEOUT,
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NULL
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);
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}
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/**
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Enable DEVSLP of the disk if supported.
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@param PciIo The PCI IO protocol instance.
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@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
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@param Port The number of port.
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@param PortMultiplier The multiplier of port.
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@param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
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@retval EFI_SUCCESS The DEVSLP is enabled per policy successfully.
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@retval EFI_UNSUPPORTED The DEVSLP isn't supported by the controller/device and policy requires to enable it.
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**/
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EFI_STATUS
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AhciEnableDevSlp (
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IN EFI_PCI_IO_PROTOCOL *PciIo,
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IN EFI_AHCI_REGISTERS *AhciRegisters,
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IN UINT8 Port,
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IN UINT8 PortMultiplier,
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IN EFI_IDENTIFY_DATA *IdentifyData
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)
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{
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EFI_STATUS Status;
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UINT32 Offset;
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UINT32 Capability2;
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UINT8 LogData[512];
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DEVSLP_TIMING_VARIABLES DevSlpTiming;
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UINT32 PortCmd;
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UINT32 PortDevSlp;
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if (mAtaAtapiPolicy->DeviceSleepEnable != 1) {
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return EFI_SUCCESS;
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}
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//
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// Do not enable DevSlp if DevSlp is not supported.
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//
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Capability2 = AhciReadReg (PciIo, AHCI_CAPABILITY2_OFFSET);
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DEBUG ((DEBUG_INFO, "AHCI CAPABILITY2 = %08x\n", Capability2));
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if ((Capability2 & AHCI_CAP2_SDS) == 0) {
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return EFI_UNSUPPORTED;
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}
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//
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// Do not enable DevSlp if DevSlp is not present
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// Do not enable DevSlp if Hot Plug or Mechanical Presence Switch is supported
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//
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Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH;
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PortCmd = AhciReadReg (PciIo, Offset + EFI_AHCI_PORT_CMD);
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PortDevSlp = AhciReadReg (PciIo, Offset + AHCI_PORT_DEVSLP);
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DEBUG ((DEBUG_INFO, "Port CMD/DEVSLP = %08x / %08x\n", PortCmd, PortDevSlp));
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if (((PortDevSlp & AHCI_PORT_DEVSLP_DSP) == 0) ||
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((PortCmd & (EFI_AHCI_PORT_CMD_HPCP | EFI_AHCI_PORT_CMD_MPSP)) != 0)
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) {
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return EFI_UNSUPPORTED;
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}
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//
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// Do not enable DevSlp if the device doesn't support DevSlp
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//
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DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
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IdentifyData->AtaData.reserved_77,
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IdentifyData->AtaData.serial_ata_features_supported, IdentifyData->AtaData.serial_ata_features_enabled));
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if ((IdentifyData->AtaData.serial_ata_features_supported & BIT8) == 0) {
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DEBUG ((DEBUG_INFO, "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
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Port, PortMultiplier));
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return EFI_UNSUPPORTED;
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}
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//
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// Enable DevSlp when it is not enabled.
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//
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if ((IdentifyData->AtaData.serial_ata_features_enabled & BIT8) != 0) {
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Status = AhciDeviceSetFeature (
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PciIo, AhciRegisters, Port, 0, ATA_SUB_CMD_ENABLE_SATA_FEATURE, 0x09, ATA_ATAPI_TIMEOUT
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);
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DEBUG ((DEBUG_INFO, "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
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Port, PortMultiplier, Status));
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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Status = AhciReadLogExt(PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
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//
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// Clear PxCMD.ST and PxDEVSLP.ADSE before updating PxDEVSLP.DITO and PxDEVSLP.MDAT.
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//
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AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd & ~EFI_AHCI_PORT_CMD_ST);
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PortDevSlp &= ~AHCI_PORT_DEVSLP_ADSE;
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AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
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//
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// Set PxDEVSLP.DETO and PxDEVSLP.MDAT to 0.
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//
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PortDevSlp &= ~AHCI_PORT_DEVSLP_DETO_MASK;
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PortDevSlp &= ~AHCI_PORT_DEVSLP_MDAT_MASK;
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AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
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DEBUG ((DEBUG_INFO, "Read Log Ext at port [%d] PortMultiplier [%d] - %r\n", Port, PortMultiplier, Status));
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if (EFI_ERROR (Status)) {
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//
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// Assume DEVSLP TIMING VARIABLES is not supported if the Identify Device Data log (30h, 8) fails
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//
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DevSlpTiming.Supported = 0;
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} else {
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CopyMem (&DevSlpTiming, &LogData[48], sizeof (DevSlpTiming));
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DEBUG ((DEBUG_INFO, "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
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DevSlpTiming.Supported, DevSlpTiming.Deto, DevSlpTiming.Madt));
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}
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//
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// Use 20ms as default DETO when DEVSLP TIMING VARIABLES is not supported or the DETO is 0.
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//
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if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Deto == 0)) {
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DevSlpTiming.Deto = 20;
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}
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//
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// Use 10ms as default MADT when DEVSLP TIMING VARIABLES is not supported or the MADT is 0.
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//
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if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Madt == 0)) {
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DevSlpTiming.Madt = 10;
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}
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PortDevSlp |= DevSlpTiming.Deto << 2;
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PortDevSlp |= DevSlpTiming.Madt << 10;
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AhciOrReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
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if (mAtaAtapiPolicy->AggressiveDeviceSleepEnable == 1) {
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if ((Capability2 & AHCI_CAP2_SADM) != 0) {
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PortDevSlp &= ~AHCI_PORT_DEVSLP_DITO_MASK;
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PortDevSlp |= (625 << 15);
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AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
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PortDevSlp |= AHCI_PORT_DEVSLP_ADSE;
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AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
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}
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}
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AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd);
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DEBUG ((DEBUG_INFO, "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
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Port, PortMultiplier, PortCmd, PortDevSlp));
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return EFI_SUCCESS;
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}
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/**
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/**
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Spin-up disk if IDD was incomplete or PUIS feature is enabled
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Spin-up disk if IDD was incomplete or PUIS feature is enabled
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@ -2689,6 +2896,13 @@ AhciModeInitialization (
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CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
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CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
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if (DeviceType == EfiIdeHarddisk) {
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if (DeviceType == EfiIdeHarddisk) {
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REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
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REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
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AhciEnableDevSlp (
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PciIo,
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AhciRegisters,
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Port,
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0,
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&Buffer
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);
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}
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}
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//
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//
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@ -1,7 +1,7 @@
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/** @file
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/** @file
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Header file for AHCI mode of ATA host controller.
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Header file for AHCI mode of ATA host controller.
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Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -29,6 +29,10 @@
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#define EFI_AHCI_MAX_PORTS 32
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#define EFI_AHCI_MAX_PORTS 32
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#define AHCI_CAPABILITY2_OFFSET 0x0024
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#define AHCI_CAP2_SDS BIT3
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#define AHCI_CAP2_SADM BIT4
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typedef struct {
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typedef struct {
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UINT32 Lower32;
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UINT32 Lower32;
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UINT32 Upper32;
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UINT32 Upper32;
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@ -182,7 +186,13 @@ typedef union {
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#define EFI_AHCI_PORT_SACT 0x0034
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#define EFI_AHCI_PORT_SACT 0x0034
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#define EFI_AHCI_PORT_CI 0x0038
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#define EFI_AHCI_PORT_CI 0x0038
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#define EFI_AHCI_PORT_SNTF 0x003C
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#define EFI_AHCI_PORT_SNTF 0x003C
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#define AHCI_PORT_DEVSLP 0x0044
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#define AHCI_PORT_DEVSLP_ADSE BIT0
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#define AHCI_PORT_DEVSLP_DSP BIT1
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#define AHCI_PORT_DEVSLP_DETO_MASK 0x000003FC
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#define AHCI_PORT_DEVSLP_MDAT_MASK 0x00007C00
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#define AHCI_PORT_DEVSLP_DITO_MASK 0x01FF8000
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#define AHCI_PORT_DEVSLP_DM_MASK 0x1E000000
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#pragma pack(1)
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#pragma pack(1)
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//
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//
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@ -283,6 +293,15 @@ typedef struct {
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UINT8 AhciUnknownFisRsvd[0x60];
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UINT8 AhciUnknownFisRsvd[0x60];
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} EFI_AHCI_RECEIVED_FIS;
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} EFI_AHCI_RECEIVED_FIS;
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typedef struct {
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UINT8 Madt : 5;
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UINT8 Reserved_5 : 3;
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UINT8 Deto;
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UINT16 Reserved_16;
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UINT32 Reserved_32 : 31;
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UINT32 Supported : 1;
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} DEVSLP_TIMING_VARIABLES;
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#pragma pack()
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#pragma pack()
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typedef struct {
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typedef struct {
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