Update input of disasmembler to support IfThen construct. Add prototype dos script to build BeagleBoard.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9936 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
@ -57,6 +57,7 @@ extern CHAR8 *gReg[];
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#define ENDIAN_FORMAT 21
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#define DATA_CBZ 22
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#define ADR_FORMAT 23
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#define IT_BLOCK 24
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// Thumb2 address modes
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#define B_T3 200
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@ -110,7 +111,7 @@ typedef struct {
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THUMB_INSTRUCTIONS gOpThumb[] = {
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// Thumb 16-bit instrucitons
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// Op Mask Format
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{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },
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{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
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{ "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
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{ "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
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{ "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
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@ -145,15 +146,15 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
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{ "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
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{ "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },
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{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
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{ "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
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{ "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
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{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
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{ "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
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{ "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
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{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
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{ "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
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{ "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
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{ "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
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@ -170,7 +171,7 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
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{ "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
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{ "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
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{ "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },
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{ "ORR" , 0x4300, 0xffc0, DATA_FORMAT5 },
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{ "POP" , 0xbc00, 0xfe00, POP_FORMAT },
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{ "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
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@ -183,26 +184,29 @@ THUMB_INSTRUCTIONS gOpThumb[] = {
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{ "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
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{ "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
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{ "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },
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{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
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{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
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{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B },
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{ "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H },
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{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
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{ "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
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{ "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
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{ "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
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{ "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
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{ "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
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{ "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
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{ "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
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{ "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
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{ "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
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{ "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
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{ "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
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{ "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
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{ "SWI" , 0xdf00, 0xff00, IMMED_8 },
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{ "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
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{ "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
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{ "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
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{ "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
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{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }
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{ "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },
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{ "IT", 0xbf00, 0xff00, IT_BLOCK }
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};
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@ -480,6 +484,7 @@ DisassembleThumbInstruction (
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IN UINT16 **OpCodePtrPtr,
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OUT CHAR8 *Buf,
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OUT UINTN Size,
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OUT UINT32 *ItBlock,
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IN BOOLEAN Extended
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)
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{
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@ -490,10 +495,12 @@ DisassembleThumbInstruction (
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UINT32 Offset;
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UINT16 Rd, Rn, Rm, Rt, Rt2;
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BOOLEAN H1, H2, imod;
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BOOLEAN ItFlag;
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UINT32 PC, Target, msbit, lsbit;
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CHAR8 *Cond;
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BOOLEAN S, J1, J2, P, U, W;
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UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
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UINT32 Mask;
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OpCodePtr = *OpCodePtrPtr;
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OpCode = **OpCodePtrPtr;
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@ -513,6 +520,14 @@ DisassembleThumbInstruction (
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// Increment by the minimum instruction size, Thumb2 could be bigger
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*OpCodePtrPtr += 1;
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// Manage IT Block ItFlag TRUE means we are in an IT block
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if (*ItBlock != 0) {
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ItFlag = TRUE;
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*ItBlock -= 1;
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} else {
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ItFlag = FALSE;
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}
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for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
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if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
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if (Extended) {
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@ -646,6 +661,31 @@ DisassembleThumbInstruction (
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Target = (OpCode & 0xff) << 2;
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
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return;
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case IT_BLOCK:
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// ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
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// ITSTATE[7:5] == cond[3:1]
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// ITSTATE[4] == 1st Instruction cond[0]
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// ITSTATE[3] == 2st Instruction cond[0]
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// ITSTATE[2] == 3st Instruction cond[0]
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// ITSTATE[1] == 4st Instruction cond[0]
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// ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
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// 1st one in ITSTATE low bits defines the number of instructions
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Mask = (OpCode & 0xf);
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if ((Mask & 0x1) == 0x1) {
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*ItBlock = 4;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E", (Mask & BIT1)?"T":"E");
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} else if ((OpCode & 0x3) == 0x2) {
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*ItBlock = 3;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E");
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} else if ((OpCode & 0x7) == 0x4) {
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*ItBlock = 2;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3)?"T":"E");
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} else if ((OpCode & 0xf) == 0x8) {
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*ItBlock = 1;
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}
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
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return;
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}
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}
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}
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@ -1001,6 +1041,7 @@ DisassembleArmInstruction (
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@param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
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@param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
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@param Extended TRUE dump hex for instruction too.
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@param ItBlock Size of IT Block
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@param Buf Buffer to sprintf disassembly into.
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@param Size Size of Buf in bytes.
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@ -1010,12 +1051,13 @@ DisassembleInstruction (
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IN UINT8 **OpCodePtr,
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IN BOOLEAN Thumb,
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IN BOOLEAN Extended,
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IN OUT UINT32 *ItBlock,
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OUT CHAR8 *Buf,
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OUT UINTN Size
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)
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{
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if (Thumb) {
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DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, Extended);
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DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, &ItBlock, Extended);
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} else {
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DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
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}
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