sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdeModulePkg/Xhci: Skip size round up for TRB during address translation

Browse Source 
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560

TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI
device/host memory address, it may exceed xHCI host memory pool and
cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate
whether to enforce 64byte size alignment and round up. For TRB case,
should set it to FALSE to skip the size round up.

Signed-off-by: Gao Cheng <gao.cheng@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
This commit is contained in:
Gao Cheng
2023-09-13 14:16:16 +08:00
committed by mergify[bot]
parent ad1c0394b1
commit f36e1ec1f0
6 changed files with 103 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@@ -589,7 +589,7 @@ XhcInitSched (
// Some 3rd party XHCI external cards don't support single 64-bytes width register access,
// So divide it to two 32-bytes width register access.
//
DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);
DcbaaPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries, TRUE);
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));
XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));
@@ -608,7 +608,7 @@ XhcInitSched (
// So we set RCS as inverted PCS init value to let Command Ring empty
//
CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;
CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);
CmdRingPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE);
ASSERT ((CmdRingPhy & 0x3F) == 0);
CmdRingPhy |= XHC_CRCR_RCS;
//
@@ -810,7 +810,7 @@ CreateEventRing (
EventRing->EventRingDequeue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
EventRing->EventRingEnqueue = (TRB_TEMPLATE *)EventRing->EventRingSeg0;
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);
DequeuePhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE);
//
// Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'
@@ -830,7 +830,7 @@ CreateEventRing (
ERSTBase->PtrHi = XHC_HIGH_32BIT (DequeuePhy);
ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;
ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);
ERSTPhy = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size, TRUE);
//
// Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)
@@ -914,7 +914,7 @@ CreateTransferRing (
//
EndTrb = (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));
EndTrb->Type = TRB_TYPE_LINK;
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof (TRB_TEMPLATE) * TrbNum, TRUE);
EndTrb->PtrLo = XHC_LOW_32BIT (PhyAddr);
EndTrb->PtrHi = XHC_HIGH_32BIT (PhyAddr);
//
@@ -1046,7 +1046,7 @@ IsTransferRingTrb (
if (CheckedTrb->Type == TRB_TYPE_LINK) {
LinkTrb = (LINK_TRB *)CheckedTrb;
PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64)LinkTrb->PtrHi, 32));
CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
CheckedTrb = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE);
ASSERT (CheckedTrb == Urb->Ring->RingSeg0);
}
}
@@ -1155,7 +1155,7 @@ XhcCheckUrbResult (
// Need convert pci device address to host address
//
PhyAddr = (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64)EvtTrb->TRBPtrHi, 32));
TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));
TRBPtr = (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE);
//
// Update the status of URB including the pending URB, the URB that is currently checked,
@@ -1260,7 +1260,7 @@ EXIT:
High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);
XhcDequeue = (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE);
if ((XhcDequeue & (~0x0F)) != (PhyAddr & (~0x0F))) {
//
@@ -2286,7 +2286,8 @@ XhcInitializeDeviceSlot (
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,
TRUE
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -2304,7 +2305,7 @@ XhcInitializeDeviceSlot (
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
// a pointer to the Output Device Context data structure (6.2.1).
//
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT), TRUE);
//
// Fill DCBAA with PCI device address
//
@@ -2319,7 +2320,7 @@ XhcInitializeDeviceSlot (
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE);
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
@@ -2510,7 +2511,8 @@ XhcInitializeDeviceSlot64 (
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,
TRUE
);
InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
@@ -2528,7 +2530,7 @@ XhcInitializeDeviceSlot64 (
// 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with
// a pointer to the Output Device Context data structure (6.2.1).
//
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, sizeof (DEVICE_CONTEXT_64), TRUE);
//
// Fill DCBAA with PCI device address
//
@@ -2543,7 +2545,7 @@ XhcInitializeDeviceSlot64 (
//
gBS->Stall (XHC_RESET_RECOVERY_DELAY);
ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE);
CmdTrbAddr.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbAddr.CycleBit = 1;
@@ -2986,7 +2988,8 @@ XhcInitializeEndpointContext (
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,
TRUE
);
PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
@@ -3188,7 +3191,8 @@ XhcInitializeEndpointContext64 (
PhyAddr = UsbHcGetPciAddrForHostAddr (
Xhc->MemPool,
((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0,
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER
sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,
TRUE
);
PhyAddr &= ~((EFI_PHYSICAL_ADDRESS)0x0F);
PhyAddr |= (EFI_PHYSICAL_ADDRESS)((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;
@@ -3270,7 +3274,7 @@ XhcSetConfigCmd (
// configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3361,7 +3365,7 @@ XhcSetConfigCmd64 (
// configure endpoint
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3535,7 +3539,7 @@ XhcSetTrDequeuePointer (
// Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
@@ -3735,7 +3739,7 @@ XhcSetInterface (
// 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -3941,7 +3945,7 @@ XhcSetInterface64 (
// 5) Issue and successfully complete a Configure Endpoint Command.
//
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4008,7 +4012,7 @@ XhcEvaluateContext (
InputContext->EP[0].EPState = 0;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE);
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -4069,7 +4073,7 @@ XhcEvaluateContext64 (
InputContext->EP[0].EPState = 0;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE);
CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbEvalu.CycleBit = 1;
@@ -4138,7 +4142,7 @@ XhcConfigHubContext (
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;
@@ -4207,7 +4211,7 @@ XhcConfigHubContext64 (
InputContext->Slot.MTT = MTT;
ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64), TRUE);
CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (PhyAddr);
CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdTrbCfgEP.CycleBit = 1;