Move SmmDebug feature from ASM to C.
SmmDebug feature is implemented in ASM, which is not easy to maintain. So we move it to C function. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18946 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -940,6 +940,65 @@ SmmStartupThisAp (
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return EFI_SUCCESS;
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}
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/**
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This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.
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They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.
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NOTE: It might not be appreciated in runtime since it might
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conflict with OS debugging facilities. Turn them off in RELEASE.
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@param CpuIndex CPU Index
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**/
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VOID
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EFIAPI
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CpuSmmDebugEntry (
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IN UINTN CpuIndex
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)
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{
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SMRAM_SAVE_STATE_MAP *CpuSaveState;
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if (FeaturePcdGet (PcdCpuSmmDebug)) {
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CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
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if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
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AsmWriteDr6 (CpuSaveState->x86._DR6);
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AsmWriteDr7 (CpuSaveState->x86._DR7);
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} else {
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AsmWriteDr6 ((UINTN)CpuSaveState->x64._DR6);
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AsmWriteDr7 ((UINTN)CpuSaveState->x64._DR7);
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}
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}
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}
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/**
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This funciton restores DR6 & DR7 to SMM save state.
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NOTE: It might not be appreciated in runtime since it might
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conflict with OS debugging facilities. Turn them off in RELEASE.
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@param CpuIndex CPU Index
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**/
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VOID
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EFIAPI
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CpuSmmDebugExit (
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IN UINTN CpuIndex
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)
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{
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SMRAM_SAVE_STATE_MAP *CpuSaveState;
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if (FeaturePcdGet (PcdCpuSmmDebug)) {
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CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
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if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
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CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
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CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();
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} else {
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CpuSaveState->x64._DR7 = AsmReadDr7 ();
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CpuSaveState->x64._DR6 = AsmReadDr6 ();
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}
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}
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}
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/**
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C function for SMI entry, each processor comes here upon SMI trigger.
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