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ArmPkg/PL35xSmc: Split the SMC initialization in multiple Chip Select initialization functions

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Some ArmVExpress-based tiles do not map all the ArmVExpress Chips into their memory map.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11797 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-06-11 11:26:42 +00:00
parent d355ba4855
commit f501f5d1b5
5 changed files with 237 additions and 158 deletions
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80
ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
View File

@@ -14,7 +14,7 @@
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <AutoGen.h> #include <AutoGen.h>
#include <AsmMacroIoLib.h> #include <Drivers/PL354Smc.h>
#Start of the code section #Start of the code section
.text .text
@@ -22,13 +22,12 @@
#Maintain 8 byte alignment #Maintain 8 byte alignment
.align 3 .align 3
#Export Initialize SMC symbol
GCC_ASM_EXPORT(InitializeSMC)
# Static memory configuation definitions for SMC GCC_ASM_EXPORT(SMCInitializeNOR)
.set SmcDirectCmd, 0x10 GCC_ASM_EXPORT(SMCInitializeSRAM)
.set SmcSetCycles, 0x14 GCC_ASM_EXPORT(SMCInitializePeripherals)
.set SmcSetOpMode, 0x18 GCC_ASM_EXPORT(SMCInitializeVRAM)
# CS0 CS0-Interf0 NOR1 flash on the motherboard # CS0 CS0-Interf0 NOR1 flash on the motherboard
# CS1 CS1-Interf0 Reserved for the motherboard # CS1 CS1-Interf0 Reserved for the motherboard
@@ -39,125 +38,134 @@ GCC_ASM_EXPORT(InitializeSMC)
# CS6 CS2-Interf1 memory-mapped peripherals # CS6 CS2-Interf1 memory-mapped peripherals
# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard. # CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
# IN r1 SmcBase // IN r1 SmcBase
# IN r2 VideoSRamBase // IN r2 ChipSelect
# NOTE: This code is been called before any stack has been setup. It means some registers // NOTE: This code is been called before any stack has been setup. It means some registers
# could be overwritten (case of 'r0') // could be overwritten (case of 'r0')
ASM_PFX(SMCInitializeNOR):
ASM_PFX(InitializeSMC):
# #
# Setup NOR1 (CS0-Interface0) # Setup NOR1 (CS0-Interface0)
# #
#Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register) # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
#Read cycle timeout = 0xA (0:3) #Read cycle timeout = 0xA (0:3)
#Write cycle timeout = 0x3(7:4) #Write cycle timeout = 0x3(7:4)
#OE Assertion Delay = 0x9(11:8) #OE Assertion Delay = 0x9(11:8)
#WE Assertion delay = 0x3(15:12) #WE Assertion delay = 0x3(15:12)
#Page cycle timeout = 0x2(19:16) #Page cycle timeout = 0x2(19:16)
LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
#Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register) # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000028 = ReadMemoryBurstLength:continuous # 0x00000028 = ReadMemoryBurstLength:continuous
# 0x00000280 = WriteMemoryBurstLength:continuous # 0x00000280 = WriteMemoryBurstLength:continuous
# 0x00000800 = Set Address Valid # 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
#Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
# 0x00000000 = ChipSelect0-Interface 0 # 0x00000000 = ChipSelect0-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000 LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
bx lr
ASM_PFX(SMCInitializeSRAM):
# #
# Setup SRAM (CS2-Interface0) # Setup SRAM (CS2-Interface0)
# #
LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158 LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000800 = Set Address Valid # 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802 LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x01000000 = ChipSelect2-Interface 0 # 0x01000000 = ChipSelect2-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000 LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
bx lr
ASM_PFX(SMCInitializePeripherals):
# #
# USB/Eth/VRAM (CS3-Interface0) # USB/Eth/VRAM (CS3-Interface0)
# #
LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous # 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous # 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x01800000 = ChipSelect3-Interface 0 # 0x01800000 = ChipSelect3-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000 LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
# #
# Setup NOR3 (CS0-Interface1) # Setup NOR3 (CS0-Interface1)
# #
LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000028 = ReadMemoryBurstLength:continuous # 0x00000028 = ReadMemoryBurstLength:continuous
# 0x00000280 = WriteMemoryBurstLength:continuous # 0x00000280 = WriteMemoryBurstLength:continuous
# 0x00000800 = Set Address Valid # 0x00000800 = Set Address Valid
LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x02000000 = ChipSelect0-Interface 1 # 0x02000000 = ChipSelect0-Interface 1
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000 LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
# #
# Setup Peripherals (CS3-Interface1) # Setup Peripherals (CS3-Interface1)
# #
LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156 LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous # 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous # 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x03800000 = ChipSelect3-Interface 1 # 0x03800000 = ChipSelect3-Interface 1
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000 LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
bx lr
// IN r1 SmcBase
// IN r2 VideoSRamBase
// NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0')
ASM_PFX(SMCInitializeVRAM):
# #
# Setup VRAM (CS1-Interface0) # Setup VRAM (CS1-Interface0)
# #
LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249 LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
# 0x00000002 = MemoryWidth: 32bit # 0x00000002 = MemoryWidth: 32bit
# 0x00000004 = Memory reads are synchronous # 0x00000004 = Memory reads are synchronous
# 0x00000040 = Memory writes are synchronous # 0x00000040 = Memory writes are synchronous
LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046 LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode] str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
# 0x00800000 = ChipSelect1-Interface 0 # 0x00800000 = ChipSelect1-Interface 0
# 0x00400000 = CmdTypes: UpdateRegs # 0x00400000 = CmdTypes: UpdateRegs
LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000 LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000
str r0, [r1, #SmcDirectCmd] str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
# #
# Page mode setup for VRAM # Page mode setup for VRAM

164
ArmPkg/Drivers/PL35xSmc/InitializeSMC.asm
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@@ -13,20 +13,19 @@
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Drivers/PL354Smc.h>
#include <AutoGen.h> #include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc INCLUDE AsmMacroIoLib.inc
EXPORT InitializeSMC EXPORT SMCInitializeNOR
EXPORT SMCInitializeSRAM
EXPORT SMCInitializePeripherals
EXPORT SMCInitializeVRAM
PRESERVE8 PRESERVE8
AREA ModuleInitializeSMC, CODE, READONLY AREA ModuleInitializeSMC, CODE, READONLY
// Static memory configuation definitions for SMC
SmcDirectCmd EQU 0x10
SmcSetCycles EQU 0x14
SmcSetOpMode EQU 0x18
// CS0 CS0-Interf0 NOR1 flash on the motherboard // CS0 CS0-Interf0 NOR1 flash on the motherboard
// CS1 CS1-Interf0 Reserved for the motherboard // CS1 CS1-Interf0 Reserved for the motherboard
// CS2 CS2-Interf0 SRAM on the motherboard // CS2 CS2-Interf0 SRAM on the motherboard
@@ -37,133 +36,104 @@ SmcSetOpMode EQU 0x18
// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard. // CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
// IN r1 SmcBase // IN r1 SmcBase
// IN r2 VideoSRamBase // IN r2 ChipSelect
// NOTE: This code is been called before any stack has been setup. It means some registers // NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0') // could be overwritten (case of 'r0')
InitializeSMC SMCInitializeNOR
// // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
// Setup NOR1 (CS0-Interface0) // - Read cycle timeout = 0xA (0:3)
// // - Write cycle timeout = 0x3(7:4)
// - OE Assertion Delay = 0x9(11:8)
//Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register) // - WE Assertion delay = 0x3(15:12)
//Read cycle timeout = 0xA (0:3) // - Page cycle timeout = 0x2(19:16)
//Write cycle timeout = 0x3(7:4)
//OE Assertion Delay = 0x9(11:8)
//WE Assertion delay = 0x3(15:12)
//Page cycle timeout = 0x2(19:16)
ldr r0, = 0x0002393A ldr r0, = 0x0002393A
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
//Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register) // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
// 0x00000002 = MemoryWidth: 32bit ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)
// 0x00000028 = ReadMemoryBurstLength:continuous str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
// 0x00000280 = WriteMemoryBurstLength:continuous
// 0x00000800 = Set Address Valid
ldr r0, = 0x00000AAA
str r0, [r1, #SmcSetOpMode]
//Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
// 0x00000000 = ChipSelect0-Interface 0 ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
// 0x00400000 = CmdTypes: UpdateRegs orr r0, r0, r2
ldr r0, = 0x00400000 str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
str r0, [r1, #SmcDirectCmd]
bx lr
// //
// Setup SRAM (CS2-Interface0) // Setup SRAM (CS2-Interface0)
// //
SMCInitializeSRAM
ldr r0, = 0x00027158 ldr r0, = 0x00027158
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
// 0x00000002 = MemoryWidth: 32bit ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)
// 0x00000800 = Set Address Valid str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
ldr r0, = 0x00000802
str r0, [r1, #SmcSetOpMode]
// 0x01000000 = ChipSelect2-Interface 0 ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))
// 0x00400000 = CmdTypes: UpdateRegs str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
ldr r0, = 0x01400000
str r0, [r1, #SmcDirectCmd]
bx lr
SMCInitializePeripherals
// //
// USB/Eth/VRAM (CS3-Interface0) // USB/Eth/VRAM (CS3-Interface0)
// //
ldr r0, = 0x000CD2AA ldr r0, = 0x000CD2AA
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
// 0x00000002 = MemoryWidth: 32bit ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
// 0x00000004 = Memory reads are synchronous str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
// 0x00000040 = Memory writes are synchronous
ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode]
// 0x01800000 = ChipSelect3-Interface 0 ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))
// 0x00400000 = CmdTypes: UpdateRegs str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
ldr r0, = 0x01C00000
str r0, [r1, #SmcDirectCmd]
//
// Setup NOR3 (CS0-Interface1)
//
ldr r0, = 0x0002393A
str r0, [r1, #SmcSetCycles]
// 0x00000002 = MemoryWidth: 32bit
// 0x00000028 = ReadMemoryBurstLength:continuous
// 0x00000280 = WriteMemoryBurstLength:continuous
// 0x00000800 = Set Address Valid
ldr r0, = 0x00000AAA
str r0, [r1, #SmcSetOpMode]
// 0x02000000 = ChipSelect0-Interface 1
// 0x00400000 = CmdTypes: UpdateRegs
ldr r0, = 0x02400000
str r0, [r1, #SmcDirectCmd]
// //
// Setup Peripherals (CS3-Interface1) // Setup Peripherals (CS3-Interface1)
// //
ldr r0, = 0x00025156 ldr r0, = 0x00025156
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
// 0x00000002 = MemoryWidth: 32bit ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
// 0x00000004 = Memory reads are synchronous str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
// 0x00000040 = Memory writes are synchronous
ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode]
// 0x03800000 = ChipSelect3-Interface 1 ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))
// 0x00400000 = CmdTypes: UpdateRegs str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
ldr r0, = 0x03C00000
str r0, [r1, #SmcDirectCmd]
// bx lr
// Setup VRAM (CS1-Interface0)
//
// IN r1 SmcBase
// IN r2 VideoSRamBase
// NOTE: This code is been called before any stack has been setup. It means some registers
// could be overwritten (case of 'r0')
SMCInitializeVRAM
//
// Setup VRAM (CS1-Interface0)
//
ldr r0, = 0x00049249 ldr r0, = 0x00049249
str r0, [r1, #SmcSetCycles] str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]
// 0x00000002 = MemoryWidth: 32bit ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)
// 0x00000004 = Memory reads are synchronous str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]
// 0x00000040 = Memory writes are synchronous
ldr r0, = 0x00000046
str r0, [r1, #SmcSetOpMode]
// 0x00800000 = ChipSelect1-Interface 0 ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))
// 0x00400000 = CmdTypes: UpdateRegs str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]
ldr r0, = 0x00C00000
str r0, [r1, #SmcDirectCmd]
// //
// Page mode setup for VRAM // Page mode setup for VRAM
// //
//read current state
// Read current state
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, = 0x00000000 ldr r0, = 0x00000000
str r0, [r2, #0] str r0, [r2, #0]
ldr r0, [r2, #0] ldr r0, [r2, #0]
//enable page mode // Enable page mode
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, = 0x00000000 ldr r0, = 0x00000000
@@ -171,7 +141,7 @@ InitializeSMC
ldr r0, = 0x00900090 ldr r0, = 0x00900090
str r0, [r2, #0] str r0, [r2, #0]
//confirm page mode enabled // Confirm page mode enabled
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, [r2, #0] ldr r0, [r2, #0]
ldr r0, = 0x00000000 ldr r0, = 0x00000000

57
ArmPkg/Include/Drivers/PL354Smc.h Normal file
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@@ -0,0 +1,57 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef PL354SMC_H_
#define PL354SMC_H_
#define PL354_SMC_DIRECT_CMD_OFFSET 0x10
#define PL354_SMC_SET_CYCLES_OFFSET 0x14
#define PL354_SMC_SET_OPMODE_OFFSET 0x18
#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))
#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)
#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)
#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)
#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
#endif

62
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.S
View File

@@ -1,36 +1,32 @@
#------------------------------------------------------------------------------ //
# // Copyright (c) 2011, ARM Limited. All rights reserved.
# ARM VE Entry point. Reset vector in FV header will brach to //
# _ModuleEntryPoint. // This program and the accompanying materials
# // are licensed and made available under the terms and conditions of the BSD License
# We use crazy macros, like LoadConstantToReg, since Xcode assembler // which accompanies this distribution. The full text of the license may be found at
# does not support = assembly syntax for ldr. // http://opensource.org/licenses/bsd-license.php
# //
# Copyright (c) 2011, ARM Limited. All rights reserved. // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
# This program and the accompanying materials //
# are licensed and made available under the terms and conditions of the BSD License //
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Base.h> #include <Base.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
#include <Drivers/PL354Smc.h>
#include <AutoGen.h> #include <AutoGen.h>
#Start of Code section
.text .text
.align 3 .align 3
GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized) GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
.extern ASM_PFX(InitializeSMC) .extern ASM_PFX(SMCInitializeNOR)
.extern ASM_PFX(SMCInitializeSRAM)
.extern ASM_PFX(SMCInitializePeripherals)
.extern ASM_PFX(SMCInitializeVRAM)
/** /**
Called at the early stage of the Boot phase to know if the memory has already been initialized Called at the early stage of the Boot phase to know if the memory has already been initialized
@@ -65,10 +61,32 @@ ASM_PFX(ArmPlatformIsMemoryInitialized):
**/ **/
ASM_PFX(ArmPlatformInitializeBootMemory): ASM_PFX(ArmPlatformInitializeBootMemory):
mov r5, lr mov r5, lr
//
// Initialize PL354 SMC // Initialize PL354 SMC
//
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
// NOR Flash 0
LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(0,0), r2)
blx ASM_PFX(SMCInitializeNOR)
// NOR Flash 1
LoadConstantToReg (PL354_SMC_DIRECT_CMD_ADDR_CS(1,0), r2)
blx ASM_PFX(SMCInitializeNOR)
// Setup SRAM
blx ASM_PFX(SMCInitializeSRAM)
// Memory Mapped Peripherals
blx ASM_PFX(SMCInitializePeripherals)
// Initialize VRAM
//TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
// It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
blx ASM_PFX(InitializeSMC) blx ASM_PFX(SMCInitializeVRAM)
bx r5 bx r5
.end .end

32
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Helper.asm
View File

@@ -15,13 +15,17 @@
#include <Base.h> #include <Base.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <ArmPlatform.h> #include <ArmPlatform.h>
#include <Drivers/PL354Smc.h>
#include <AutoGen.h> #include <AutoGen.h>
INCLUDE AsmMacroIoLib.inc INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformIsMemoryInitialized EXPORT ArmPlatformIsMemoryInitialized
EXPORT ArmPlatformInitializeBootMemory EXPORT ArmPlatformInitializeBootMemory
IMPORT InitializeSMC IMPORT SMCInitializeNOR
IMPORT SMCInitializeSRAM
IMPORT SMCInitializePeripherals
IMPORT SMCInitializeVRAM
PRESERVE8 PRESERVE8
AREA CTA9x4Helper, CODE, READONLY AREA CTA9x4Helper, CODE, READONLY
@@ -59,10 +63,32 @@ ArmPlatformIsMemoryInitialized
**/ **/
ArmPlatformInitializeBootMemory ArmPlatformInitializeBootMemory
mov r5, lr mov r5, lr
//
// Initialize PL354 SMC // Initialize PL354 SMC
//
LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
// NOR Flash 0
mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(0,0)
blx SMCInitializeNOR
// NOR Flash 1
mov r2, PL354_SMC_DIRECT_CMD_ADDR_CS(1,0)
blx SMCInitializeNOR
// Setup SRAM
blx SMCInitializeSRAM
// Memory Mapped Peripherals
blx SMCInitializePeripherals
// Initialize VRAM
//TODO: Check if we really must inititialize Video SRAM in UEFI. Does Linux can do it ? Does the Video driver can do it ?
// It will be faster (only initialize if required) and easier (remove assembly code because of a stack available) to move this initialization.
LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
blx InitializeSMC blx SMCInitializeVRAM
bx r5 bx r5
END END