sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

FmpDevicePkg: Fix various typos

Browse Source 
Fix one typo in FmpDevicePkg.

Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
This commit is contained in:
Antoine Cœur
2019-07-09 17:10:11 +08:00
committed by Chasel Chiu
parent 8a842b31b9
commit f527942e6b
18 changed files with 52 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
View File

@@ -194,9 +194,9 @@ StackSetupDone:
;
; Pass BFV into the PEI Core
; It uses relative address to calucate the actual boot FV base
; It uses relative address to calculate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
; they are different. The code below can handle both cases.
;
call ASM_PFX(AsmGetFspBaseAddress)

4
IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits):
fldcw [ASM_PFX(mFpuControlWord)]
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1

4
IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -150,7 +150,7 @@ NextAddress:
fldcw [FpuControlWord]
;
; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1

4
IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack):
mov esp, eax ; From now, esp is pointed to permanent memory
;
; Fixup the ebp point to permenent memory
; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx

4
IntelFsp2Pkg/FspSecCore/SecFsp.c
View File

@@ -1,6 +1,6 @@
/** @file
Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -169,7 +169,7 @@ FspGlobalDataInit (
SerialPortInitialize ();
//
// Ensure the golbal data pointer is valid
// Ensure the global data pointer is valid
//
ASSERT (GetFspGlobalDataPointer () == PeiFspData);

2
IntelFsp2Pkg/FspSecCore/SecMain.c
View File

@@ -110,7 +110,7 @@ SecStartup (
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | Heap | PeiTemporaryRamSize
// | |
// | |
// |-------------------|----> TempRamBase

4
IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
View File

@@ -2,7 +2,7 @@
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;;
@@ -61,7 +61,7 @@ ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
; SEC entry point relatvie address will be fixed up by some build tool.
; SEC entry point relative address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm