ArmPlatformPkg: Code cleaning
- Fix coding style to follow EDK2 coding convention - Remove deprecated function - Remove unused PCDs git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11808 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
@@ -12,13 +12,14 @@
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*
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmMPCoreMailBoxLib.h>
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#include <Chipset/ArmV7.h>
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#include <Drivers/PL390Gic.h>
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#include "PrePeiCore.h"
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extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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/*
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@@ -32,60 +33,64 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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*/
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VOID
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EFIAPI
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secondary_main(IN UINTN CoreId)
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SecondaryMain (
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IN UINTN CoreId
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)
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{
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//Function pointer to Secondary Core entry point
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VOID (*secondary_start)(VOID);
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UINTN secondary_entry_addr=0;
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// Function pointer to Secondary Core entry point
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VOID (*secondary_start)(VOID);
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UINTN secondary_entry_addr=0;
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//Clear Secondary cores MailBox
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ArmClearMPCoreMailbox();
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// Clear Secondary cores MailBox
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ArmClearMPCoreMailbox();
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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//Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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}
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while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
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ArmCallWFI();
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// Acknowledge the interrupt and send End of Interrupt signal.
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PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
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}
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secondary_start = (VOID (*)())secondary_entry_addr;
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secondary_start = (VOID (*)())secondary_entry_addr;
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//Jump to secondary core entry point.
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secondary_start();
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// Jump to secondary core entry point.
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secondary_start();
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//the secondaries shouldn't reach here
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ASSERT(FALSE);
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// The secondaries shouldn't reach here
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ASSERT(FALSE);
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}
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VOID primary_main (
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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//Enable the GIC Distributor
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PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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//Enable the GIC Distributor
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PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
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// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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// Sending SGI to all the Secondary CPU interfaces
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
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if (FeaturePcdGet(PcdStandalone) == FALSE) {
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// Sending SGI to all the Secondary CPU interfaces
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PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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// jump to pei core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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// Jump to PEI core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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}
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@@ -12,42 +12,47 @@
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*
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**/
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#include <PiPei.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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#include "PrePeiCore.h"
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extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
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VOID
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EFIAPI
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secondary_main(IN UINTN CoreId)
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SecondaryMain (
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IN UINTN CoreId
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)
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{
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ASSERT(FALSE);
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ASSERT(FALSE);
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}
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VOID primary_main (
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);
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SecCoreData.PeiTemporaryRamBase = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));
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SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;
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SecCoreData.StackBase = SecCoreData.TemporaryRamBase;
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SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
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// jump to pei core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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// jump to pei core entry point
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(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);
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}
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@@ -13,29 +13,17 @@
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*
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**/
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#include <PiPei.h>
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#include <Ppi/TemporaryRamSupport.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PrintLib.h>
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#include <Library/ArmLib.h>
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#include <Library/SerialPortLib.h>
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#include <Chipset/ArmV7.h>
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EFI_STATUS
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EFIAPI
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SecTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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);
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VOID
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SecSwitchStack (
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INTN StackDelta
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);
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#include "PrePeiCore.h"
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EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
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@@ -47,10 +35,6 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
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}
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};
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// Vector Table for Pei Phase
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VOID PeiVectorTable (VOID);
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VOID
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CEntryPoint (
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IN UINTN CoreId,
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@@ -64,8 +48,8 @@ CEntryPoint (
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ArmInvalidateInstructionCache();
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// Enable Instruction & Data caches
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ArmEnableDataCache();
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ArmEnableInstructionCache();
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ArmEnableDataCache ();
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ArmEnableInstructionCache ();
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//
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// Note: Doesn't have to Enable CPU interface in non-secure world,
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@@ -81,9 +65,9 @@ CEntryPoint (
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//If not primary Jump to Secondary Main
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if(0 == CoreId) {
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//Goto primary Main.
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primary_main(PeiCoreEntryPoint);
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PrimaryMain (PeiCoreEntryPoint);
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} else {
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secondary_main(CoreId);
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SecondaryMain (CoreId);
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}
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// PEI Core should always load and never return
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@@ -101,7 +85,7 @@ SecTemporaryRamSupport (
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{
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//
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// Migrate the whole temporary memory to permenent memory.
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//
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//
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CopyMem (
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(VOID*)(UINTN)PermanentMemoryBase,
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(VOID*)(UINTN)TemporaryMemoryBase,
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60
ArmPlatformPkg/PrePeiCore/PrePeiCore.h
Normal file
60
ArmPlatformPkg/PrePeiCore/PrePeiCore.h
Normal file
@@ -0,0 +1,60 @@
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/** @file
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* Main file supporting the transition to PEI Core in Normal World for Versatile Express
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PREPEICORE_H_
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#define __PREPEICORE_H_
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#include <PiPei.h>
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#include <Ppi/TemporaryRamSupport.h>
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EFI_STATUS
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EFIAPI
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SecTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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);
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VOID
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SecSwitchStack (
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INTN StackDelta
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);
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// Vector Table for Pei Phase
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VOID PeiVectorTable (VOID);
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VOID
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EFIAPI
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PrimaryMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
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);
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/*
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* This is the main function for secondary cores. They loop around until a non Null value is written to
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* SYS_FLAGS register.The SYS_FLAGS register is platform specific.
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* Note:The secondary cores, while executing secondary_main, assumes that:
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* : SGI 0 is configured as Non-secure interrupt
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* : Priority Mask is configured to allow SGI 0
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* : Interrupt Distributor and CPU interfaces are enabled
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*
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*/
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VOID
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EFIAPI
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SecondaryMain (
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IN UINTN CoreId
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);
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#endif
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