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UefiCpuPkg/SmmCpuFeaturesLib: Skip SMBASE configuration

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4337

This patch is to avoid configure SMBASE if SmBase relocation has been
done. If gSmmBaseHobGuid found, means SmBase info has been relocated
and recorded in the SmBase array. No need to do the relocation in
SmmCpuFeaturesInitializeProcessor().

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Wu, Jiaxin
2023-02-16 14:16:32 +08:00
committed by mergify[bot]
parent ec07fd0e35
commit f6b86eec5a
6 changed files with 36 additions and 9 deletions
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25
UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
View File

@@ -1,7 +1,7 @@
/** @file
Implementation shared across all library instances.
Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -38,6 +38,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;
//
// Indicate SmBase for each Processors has been relocated or not. If TRUE,
// means no need to do the relocation in SmmCpuFeaturesInitializeProcessor().
//
BOOLEAN mSmmCpuFeaturesSmmRelocated;
//
// Set default value to assume MTRRs need to be configured on each SMI
//
@@ -144,6 +150,12 @@ CpuFeaturesLibInitialization (
//
mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * GetCpuMaxLogicalProcessorNumber ());
ASSERT (mSmrrEnabled != NULL);
//
// If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded
// in the SmBase array.
//
mSmmCpuFeaturesSmmRelocated = (BOOLEAN)(GetFirstGuidHob (&gSmmBaseHobGuid) != NULL);
}
/**
@@ -187,10 +199,15 @@ SmmCpuFeaturesInitializeProcessor (
UINTN ModelId;
//
// Configure SMBASE.
// No need to configure SMBASE if SmBase relocation has been done.
//
CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
if (!mSmmCpuFeaturesSmmRelocated) {
//
// Configure SMBASE.
//
CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
}
//
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual