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BaseTools: Clean up source files

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Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
This commit is contained in:
Liming Gao
2018-07-05 17:40:04 +08:00
parent 39456d00f3
commit f7496d7173
289 changed files with 10647 additions and 10647 deletions
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114
BaseTools/Source/C/Common/PeCoffLoaderEx.c
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@ -1,15 +1,15 @@
/** @file
IA32, X64 and IPF Specific relocation fixups
Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
--*/
@ -27,45 +27,45 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
#define IMM64_IMM7B_INST_WORD_X 3
#define IMM64_IMM7B_SIZE_X 7
#define IMM64_IMM7B_INST_WORD_POS_X 4
#define IMM64_IMM7B_VAL_POS_X 0
#define IMM64_IMM7B_INST_WORD_X 3
#define IMM64_IMM7B_SIZE_X 7
#define IMM64_IMM7B_INST_WORD_POS_X 4
#define IMM64_IMM7B_VAL_POS_X 0
#define IMM64_IMM9D_INST_WORD_X 3
#define IMM64_IMM9D_SIZE_X 9
#define IMM64_IMM9D_INST_WORD_POS_X 18
#define IMM64_IMM9D_VAL_POS_X 7
#define IMM64_IMM9D_INST_WORD_X 3
#define IMM64_IMM9D_SIZE_X 9
#define IMM64_IMM9D_INST_WORD_POS_X 18
#define IMM64_IMM9D_VAL_POS_X 7
#define IMM64_IMM5C_INST_WORD_X 3
#define IMM64_IMM5C_SIZE_X 5
#define IMM64_IMM5C_INST_WORD_POS_X 13
#define IMM64_IMM5C_VAL_POS_X 16
#define IMM64_IMM5C_INST_WORD_X 3
#define IMM64_IMM5C_SIZE_X 5
#define IMM64_IMM5C_INST_WORD_POS_X 13
#define IMM64_IMM5C_VAL_POS_X 16
#define IMM64_IC_INST_WORD_X 3
#define IMM64_IC_SIZE_X 1
#define IMM64_IC_INST_WORD_POS_X 12
#define IMM64_IC_VAL_POS_X 21
#define IMM64_IC_INST_WORD_X 3
#define IMM64_IC_SIZE_X 1
#define IMM64_IC_INST_WORD_POS_X 12
#define IMM64_IC_VAL_POS_X 21
#define IMM64_IMM41a_INST_WORD_X 1
#define IMM64_IMM41a_SIZE_X 10
#define IMM64_IMM41a_INST_WORD_POS_X 14
#define IMM64_IMM41a_VAL_POS_X 22
#define IMM64_IMM41a_INST_WORD_X 1
#define IMM64_IMM41a_SIZE_X 10
#define IMM64_IMM41a_INST_WORD_POS_X 14
#define IMM64_IMM41a_VAL_POS_X 22
#define IMM64_IMM41b_INST_WORD_X 1
#define IMM64_IMM41b_SIZE_X 8
#define IMM64_IMM41b_INST_WORD_POS_X 24
#define IMM64_IMM41b_VAL_POS_X 32
#define IMM64_IMM41b_INST_WORD_X 1
#define IMM64_IMM41b_SIZE_X 8
#define IMM64_IMM41b_INST_WORD_POS_X 24
#define IMM64_IMM41b_VAL_POS_X 32
#define IMM64_IMM41c_INST_WORD_X 2
#define IMM64_IMM41c_SIZE_X 23
#define IMM64_IMM41c_INST_WORD_POS_X 0
#define IMM64_IMM41c_VAL_POS_X 40
#define IMM64_IMM41c_INST_WORD_X 2
#define IMM64_IMM41c_SIZE_X 23
#define IMM64_IMM41c_INST_WORD_POS_X 0
#define IMM64_IMM41c_VAL_POS_X 40
#define IMM64_SIGN_INST_WORD_X 3
#define IMM64_SIGN_SIZE_X 1
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
#define IMM64_SIGN_INST_WORD_X 3
#define IMM64_SIGN_SIZE_X 1
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
RETURN_STATUS
PeCoffLoaderRelocateIa32Image (
@ -102,7 +102,7 @@ Returns:
RETURN_STATUS
PeCoffLoaderRelocateIpfImage (
IN UINT16 *Reloc,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 *Fixup,
IN OUT CHAR8 **FixupData,
IN UINT64 Adjust
)
@ -142,8 +142,8 @@ Returns:
Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
FixupVal = (UINT64)0;
//
//
// Extract the lower 32 bits of IMM64 from bundle
//
EXT_IMM64(FixupVal,
@ -180,13 +180,13 @@ Returns:
IMM64_IMM41a_INST_WORD_POS_X,
IMM64_IMM41a_VAL_POS_X
);
//
//
// Update 64-bit address
//
FixupVal += Adjust;
//
//
// Insert IMM64 into bundle
//
INS_IMM64(FixupVal,
@ -261,7 +261,7 @@ Returns:
}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and
return the immediate data encoded in the instruction
@param Instruction Pointer to ARM MOVT or MOVW immediate instruction
@ -279,7 +279,7 @@ ThumbMovtImmediateAddress (
// Thumb2 is two 16-bit instructions working together. Not a single 32-bit instruction
// Example MOVT R0, #0 is 0x0000f2c0 or 0xf2c0 0x0000
Movt = (*Instruction << 16) | (*(Instruction + 1));
Movt = (*Instruction << 16) | (*(Instruction + 1));
// imm16 = imm4:i:imm3:imm8
// imm4 -> Bit19:Bit16
@ -308,7 +308,7 @@ ThumbMovtImmediatePatch (
UINT16 Patch;
// First 16-bit chunk of instruciton
Patch = ((Address >> 12) & 0x000f); // imm4
Patch = ((Address >> 12) & 0x000f); // imm4
Patch |= (((Address & BIT11) != 0) ? BIT10 : 0); // i
*Instruction = (*Instruction & ~0x040f) | Patch;
@ -320,7 +320,7 @@ ThumbMovtImmediatePatch (
}
/**
Pass in a pointer to an ARM MOVW/MOVT instruciton pair and
Pass in a pointer to an ARM MOVW/MOVT instruciton pair and
return the immediate data encoded in the two` instruction
@param Instructions Pointer to ARM MOVW/MOVT insturction pair
@ -336,10 +336,10 @@ ThumbMovwMovtImmediateAddress (
{
UINT16 *Word;
UINT16 *Top;
Word = Instructions; // MOVW
Top = Word + 2; // MOVT
return (ThumbMovtImmediateAddress (Top) << 16) + ThumbMovtImmediateAddress (Word);
}
@ -359,7 +359,7 @@ ThumbMovwMovtImmediatePatch (
{
UINT16 *Word;
UINT16 *Top;
Word = (UINT16 *)Instructions; // MOVW
Top = Word + 2; // MOVT
@ -394,19 +394,19 @@ PeCoffLoaderRelocateArmImage (
Fixup16 = (UINT16 *) Fixup;
switch ((**Reloc) >> 12) {
case EFI_IMAGE_REL_BASED_ARM_MOV32T:
FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;
ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);
if (*FixupData != NULL) {
*FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
CopyMem (*FixupData, Fixup16, sizeof (UINT64));
*FixupData = *FixupData + sizeof(UINT64);
}
break;
case EFI_IMAGE_REL_BASED_ARM_MOV32A:
// break omitted - ARM instruction encoding not implemented
default: