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MdePkg/Register/Amd: realign macros with more space for future expansion

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BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Version 2 of the GHCB spec introduces several new SNP-specific NAEs.
Unfortunately, the names for those NAEs break the alignment. Add some
white spaces so that the SNP support patches do not break the alignment.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
This commit is contained in:
Brijesh Singh
2021-05-19 13:19:38 -05:00
committed by mergify[bot]
parent 0095070e70
commit f828fc9876
2 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
MdePkg/Include/Register/Amd/Fam17Msr.h
View File

@@ -53,11 +53,11 @@ typedef union {
UINT64 GhcbPhysicalAddress; UINT64 GhcbPhysicalAddress;
} MSR_SEV_ES_GHCB_REGISTER; } MSR_SEV_ES_GHCB_REGISTER;
#define GHCB_INFO_SEV_INFO 1 #define GHCB_INFO_SEV_INFO 1
#define GHCB_INFO_SEV_INFO_GET 2 #define GHCB_INFO_SEV_INFO_GET 2
#define GHCB_INFO_CPUID_REQUEST 4 #define GHCB_INFO_CPUID_REQUEST 4
#define GHCB_INFO_CPUID_RESPONSE 5 #define GHCB_INFO_CPUID_RESPONSE 5
#define GHCB_INFO_TERMINATE_REQUEST 256 #define GHCB_INFO_TERMINATE_REQUEST 256
#define GHCB_TERMINATE_GHCB 0 #define GHCB_TERMINATE_GHCB 0
#define GHCB_TERMINATE_GHCB_GENERAL 0 #define GHCB_TERMINATE_GHCB_GENERAL 0

12
MdePkg/Include/Register/Amd/Ghcb.h
View File

@@ -49,12 +49,12 @@
// //
// VMG Special Exit Codes // VMG Special Exit Codes
// //
#define SVM_EXIT_MMIO_READ 0x80000001ULL #define SVM_EXIT_MMIO_READ 0x80000001ULL
#define SVM_EXIT_MMIO_WRITE 0x80000002ULL #define SVM_EXIT_MMIO_WRITE 0x80000002ULL
#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL #define SVM_EXIT_NMI_COMPLETE 0x80000003ULL
#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL #define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL
#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL #define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL
#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL #define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL
// //
// IOIO Exit Information // IOIO Exit Information