ArmPlatformPkg: Added Aarch64 Foundation Model
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14495 6f19259b-4bc3-4df7-8a09-765794883524
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Harry Liebel
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oliviermartin
oliviermartin
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/*
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* boot.S - simple register setup code for junping to a second stage bootloader
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*
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* Copyright (C) 2011-2013 ARM Limited.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of ARM nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This license can also be found in the LICENSE.TXT file.
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*/
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.text
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.globl _start
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.set LED_ADDR, 0x1c010008
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_start:
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/*
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* EL3 initialisation
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*/
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// Set LED to show progress.
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ldr x1, =LED_ADDR
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mov w0, #0x1
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str w0, [x1]
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dsb sy
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#if defined START_EL2
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mrs x0, CurrentEL
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cmp x0, #0xc // EL3?
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b.ne start_ns // skip EL3 initialisation
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mov x0, #0x30 // RES1
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orr x0, x0, #(1 << 0) // Non-secure EL1
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orr x0, x0, #(1 << 8) // HVC enable
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orr x0, x0, #(1 << 10) // 64-bit EL2
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msr scr_el3, x0
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msr cptr_el3, xzr // Disable copro. traps to EL3
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ldr x0, =CNTFRQ
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msr cntfrq_el0, x0
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/*
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* Check for the primary CPU to avoid a race on the distributor
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* registers.
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*/
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mrs x0, mpidr_el1
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tst x0, #15
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b.ne 1f // secondary CPU
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ldr x1, =GIC_DIST_BASE // GICD_CTLR
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
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mov w0, #~0 // Grp1 interrupts
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str w0, [x1], #4
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b.ne 2f // Only local interrupts for secondary CPUs
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str w0, [x1], #4
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str w0, [x1], #4
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2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
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ldr w0, [x1]
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mov w0, #3 // EnableGrp0 | EnableGrp1
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str w0, [x1]
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mov w0, #1 << 7 // allow NS access to GICC_PMR
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str w0, [x1, #4] // GICC_PMR
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msr sctlr_el2, xzr
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#if defined START_EL1
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/* Now setup our EL1. Controlled by EL2 config on Model */
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mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
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orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
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// Send all interrupts to their respective Exception levels for EL2
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bic x0, x0, #(1 << 3) // Disable virtual FIQ
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bic x0, x0, #(1 << 4) // Disable virtual IRQ
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bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
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msr hcr_el2, x0 // Write back our settings
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/*
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* Enable architected timer access
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*/
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mrs x0, cnthctl_el2
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orr x0, x0, #3 // Enable EL1 access to timers
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msr cnthctl_el2, x0
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mrs x0, cntkctl_el1
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orr x0, x0, #3 // EL0 access to counters
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msr cntkctl_el1, x0
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/* Set ID regs */
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mrs x0, midr_el1
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mrs x1, mpidr_el1
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msr vpidr_el2, x0
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msr vmpidr_el2, x1
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/* Coprocessor traps. */
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mov x0, #0x33ff
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msr cptr_el2, x0 // Disable copro. traps to EL2
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msr hstr_el2, xzr // Disable CP15 traps to EL2
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#endif // START_EL1
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/* Configure UART. Primary CPU only */
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mrs x4, mpidr_el1
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tst x4, #15
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b.ne 1f
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/*
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* UART initialisation (38400 8N1)
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*/
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ldr x4, =UART_BASE // UART base
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mov w5, #0x10 // ibrd
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str w5, [x4, #0x24]
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mov w5, #0xc300
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orr w5, w5, #0x0001 // cr
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str w5, [x4, #0x30]
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/*
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* Prepare the switch to the EL2_SP2 mode from EL3
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*/
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1: ldr x0, =start_ns // Return after mode switch
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#if defined START_EL1
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mov x1, #0x3c5 // EL1_SP1 | D | A | I | F
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#else
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mov x1, #0x3c9 // EL2_SP2 | D | A | I | F
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#endif
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msr elr_el3, x0
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msr spsr_el3, x1
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eret
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#endif // START_EL2
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start_ns:
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/*
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* We do not have NOR flash on the Foundation model. So run UEFI from RAM.
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* On the full model we use the NOR FLASH to store UEFI, so start there.
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*/
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#if defined FOUNDATION_MODEL
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mov x0, #0xa0000000
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#else
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mov x0, #0x0
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#endif
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br x0
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.ltorg
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.org 0x200
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