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Revert "Always set WP in CR0."

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This reverts SVN r18960 / git commit
8e496a7abc.

The patch series had been fully reviewed on edk2-devel, but it got
committed as a single squashed patch. Revert it for now.

Link: http://thread.gmane.org/gmane.comp.bios.edk2.devel/4951
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18977 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
2015-11-27 12:00:26 +00:00
committed by lersek
parent 83886d746e
commit fc8c919525
9 changed files with 24 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
View File

@@ -127,7 +127,7 @@ SmmInitPageTable (
// Fill Page-Table-Level4 (PML4) entry
//
PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (PAGE_TABLE_PAGES + 1));
*PTEntry = Pages + PAGE_ATTRIBUTE_BITS;
*PTEntry = Pages + IA32_PG_P;
ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
//
// Set sub-entries number
@@ -591,7 +591,7 @@ SmiDefaultPFHandler (
//
// If the entry is not present, allocate one page from page pool for it
//
PageTable[PTIndex] = AllocPage () | PAGE_ATTRIBUTE_BITS;
PageTable[PTIndex] = AllocPage () | IA32_PG_RW | IA32_PG_P;
} else {
//
// Save the upper entry address
@@ -621,7 +621,7 @@ SmiDefaultPFHandler (
// Fill the new entry
//
PageTable[PTIndex] = (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)) |
PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS;
PageAttribute | IA32_PG_A | IA32_PG_RW | IA32_PG_P;
if (UpperEntry != NULL) {
SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1);
}

2
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
View File

@@ -144,7 +144,7 @@ Base:
orb $1,%ah
wrmsr
movq %cr0, %rbx
orl $0x080010000, %ebx # enable paging + WP
btsl $31, %ebx
movq %rbx, %cr0
retf
LongMode: # long mode (64-bit code) starts here

2
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
View File

@@ -140,7 +140,7 @@ Base:
or ah, 1
wrmsr
mov rbx, cr0
or ebx, 080010000h ; enable paging + WP
bts ebx, 31
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here

12
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
View File

@@ -51,7 +51,7 @@ InitSmmS3Cr3 (
// Fill Page-Table-Level4 (PML4) entry
//
PTEntry = (UINT64*)(UINTN)(Pages - EFI_PAGES_TO_SIZE (1));
*PTEntry = Pages | PAGE_ATTRIBUTE_BITS;
*PTEntry = Pages + IA32_PG_P;
ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
//
@@ -117,7 +117,7 @@ AcquirePage (
//
// Link & Record the current uplink
//
*Uplink = Address | PAGE_ATTRIBUTE_BITS;
*Uplink = Address | IA32_PG_P | IA32_PG_RW;
mPFPageUplink[mPFPageIndex] = Uplink;
mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;
@@ -242,9 +242,9 @@ RestorePageTableAbove4G (
// PTE
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
for (Index = 0; Index < 512; Index++) {
PageTable[Index] = Address | PAGE_ATTRIBUTE_BITS;
PageTable[Index] = Address | IA32_PG_RW | IA32_PG_P;
if (!IsAddressValid (Address, &Nx)) {
PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
}
if (Nx && mXdSupported) {
PageTable[Index] = PageTable[Index] | IA32_PG_NX;
@@ -262,7 +262,7 @@ RestorePageTableAbove4G (
//
// Patch to remove present flag and rw flag.
//
PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~(IA32_PG_RW | IA32_PG_P));
}
//
// Set XD bit to 1
@@ -289,7 +289,7 @@ RestorePageTableAbove4G (
//
// Add present flag or clear XD flag to make page fault handler succeed.
//
PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);
PageTable[PTIndex] |= (UINT64)(IA32_PG_RW | IA32_PG_P);
if ((ErrorCode & IA32_PF_EC_ID) != 0) {
//
// If page fault is caused by instruction fetch, clear XD bit in the entry.