sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MdeModulePkg/PciBus: Correct typos

Browse Source 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Ray Ni
2019-02-12 11:39:02 +08:00
parent 1f6785c4b7
commit fcdfcdbfc2
20 changed files with 154 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
View File

@@ -1,7 +1,7 @@
/** @file
PCI emumeration support functions implementation for PCI Bus module.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -88,7 +88,7 @@ PciDevicePresent (
root bridge will then be created.
@param Bridge Parent bridge instance.
@param StartBusNumber Bus number of begining.
@param StartBusNumber Bus number of beginning.
@retval EFI_SUCCESS PCI device is found.
@retval other Some error occurred when reading PCI bridge information.
@@ -208,7 +208,7 @@ PciPciDeviceInfoCollector (
}
/**
Seach required device and create PCI device instance.
Search required device and create PCI device instance.
@param Bridge Parent bridge instance.
@param Pci Input PCI device information block.
@@ -370,14 +370,14 @@ DumpPpbPaddingResource (
if (Descriptor->AddrSpaceGranularity == 32) {
//
// prefechable
// prefetchable
//
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {
Type = PciBarTypePMem32;
}
//
// Non-prefechable
// Non-prefetchable
//
if (Descriptor->SpecificFlag == 0) {
Type = PciBarTypeMem32;
@@ -386,14 +386,14 @@ DumpPpbPaddingResource (
if (Descriptor->AddrSpaceGranularity == 64) {
//
// prefechable
// prefetchable
//
if (Descriptor->SpecificFlag == EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) {
Type = PciBarTypePMem64;
}
//
// Non-prefechable
// Non-prefetchable
//
if (Descriptor->SpecificFlag == 0) {
Type = PciBarTypeMem64;
@@ -568,7 +568,7 @@ GatherPpbInfo (
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
//
// Initalize the bridge control register
// Initialize the bridge control register
//
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCI_BRIDGE_CONTROL_BITS_OWNED);
@@ -722,7 +722,7 @@ GatherP2CInfo (
PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, EFI_PCI_COMMAND_BITS_OWNED);
//
// Initalize the bridge control register
// Initialize the bridge control register
//
PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, EFI_PCCARD_BRIDGE_CONTROL_BITS_OWNED);
}
@@ -746,7 +746,7 @@ GatherP2CInfo (
}
/**
Create device path for pci deivce.
Create device path for pci device.
@param ParentDevicePath Parent bridge's path.
@param PciIoDevice Pci device instance.
@@ -922,7 +922,7 @@ BarExisted (
@param PciIoDevice Pci device instance.
@param Command Input command register value, and
returned supported register value.
@param BridgeControl Inout bridge control value for PPB or P2C, and
@param BridgeControl Input bridge control value for PPB or P2C, and
returned supported bridge control value.
@param OldCommand Returned and stored old command register offset.
@param OldBridgeControl Returned and stored old Bridge control value for PPB or P2C.
@@ -1205,7 +1205,7 @@ DetermineDeviceAttribute (
EFI_STATUS Status;
//
// For Root Bridge, just copy it by RootBridgeIo proctocol
// For Root Bridge, just copy it by RootBridgeIo protocol
// so as to keep consistent with the actual attribute
//
if (PciIoDevice->Parent == NULL) {
@@ -1282,7 +1282,7 @@ DetermineDeviceAttribute (
return Status;
}
//
// Detect Fast Bact to Bact support for the device under the bridge
// Detect Fast Back to Back support for the device under the bridge
//
Status = GetFastBackToBackSupport (Temp, PCI_PRIMARY_STATUS_OFFSET);
if (FastB2BSupport && EFI_ERROR (Status)) {
@@ -1695,7 +1695,7 @@ PciIovParseVfBar (
}
//
// Fix the length to support some spefic 64 bit BAR
// Fix the length to support some special 64 bit BAR
//
Value |= ((UINT32) -1 << HighBitSet32 (Value));
@@ -1822,7 +1822,7 @@ PciParseBar (
}
//
// Workaround. Some platforms inplement IO bar with 0 length
// Workaround. Some platforms implement IO bar with 0 length
// Need to treat it as no-bar
//
if (PciIoDevice->PciBar[BarIndex].Length == 0) {
@@ -1906,7 +1906,7 @@ PciParseBar (
}
//
// Fix the length to support some spefic 64 bit BAR
// Fix the length to support some special 64 bit BAR
//
if (Value == 0) {
DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 BAR returns 0, change to 0xFFFFFFFF.\n"));
@@ -1987,7 +1987,7 @@ InitializePciDevice (
//
// Put all the resource apertures
// Resource base is set to all ones so as to indicate its resource
// has not been alloacted
// has not been allocated
//
for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne);
@@ -2077,10 +2077,10 @@ InitializeP2C (
}
/**
Create and initiliaze general PCI I/O device instance for
Create and initialize general PCI I/O device instance for
PCI device/bridge device/hotplug bridge device.
@param PciRootBridgeIo Pointer to instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
@param Bridge Parent bridge instance.
@param Pci Input Pci information block.
@param Bus Device Bus NO.
@param Device Device device NO.
@@ -2443,7 +2443,7 @@ PciEnumeratorLight (
}
//
// Record the root bridgeio protocol
// Record the root bridge-io protocol
//
RootBridgeDev->PciRootBridgeIo = PciRootBridgeIo;
@@ -2476,7 +2476,7 @@ PciEnumeratorLight (
} else {
//
// If unsuccessly, destroy the entire node
// If unsuccessfully, destroy the entire node
//
DestroyRootBridge (RootBridgeDev);
}