sravan/system76-edk2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove unrecognized chars in comment for all source C/h files.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@5354 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
qhuang8
2008-06-19 11:15:44 +00:00
parent d33ef4e7c6
commit fd0d281b3c
17 changed files with 57 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGlueBaseLib.h
View File

@@ -4577,9 +4577,9 @@ AsmReadDbr (
All processor implementations provide at least 4 performance counters
(PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter overflow
status registers (PMC [0]<EFBFBD><EFBFBD> PMC [3]). Processor implementations may provide
status registers (PMC [0]... PMC [3]). Processor implementations may provide
additional implementation-dependent PMC and PMD to increase the number of
<EFBFBD><EFBFBD>generic<EFBFBD><EFBFBD> performance counters (PMC/PMD pairs). The remainder of PMC and PMD
'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD
register set is implementation dependent. No parameter checking is performed
on Index. If the Index value is beyond the implemented PMC register range,
zero value will be returned.
@@ -4603,9 +4603,9 @@ AsmReadPmc (
All processor implementations provide at least 4 performance counters
(PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter
overflow status registers (PMC [0]<EFBFBD><EFBFBD> PMC [3]). Processor implementations may
overflow status registers (PMC [0]... PMC [3]). Processor implementations may
provide additional implementation-dependent PMC and PMD to increase the number
of <EFBFBD><EFBFBD>generic<EFBFBD><EFBFBD> performance counters (PMC/PMD pairs). The remainder of PMC and PMD
of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD
register set is implementation dependent. No parameter checking is performed
on Index. If the Index value is beyond the implemented PMD register range,
zero value will be returned.
@@ -4685,8 +4685,8 @@ AsmWriteDbr (
Writes current value of Performance Monitor Configuration Register specified by Index.
All processor implementations provide at least 4 performance counters
(PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter overflow status
registers (PMC [0]<EFBFBD><EFBFBD> PMC [3]). Processor implementations may provide additional
implementation-dependent PMC and PMD to increase the number of <EFBFBD><EFBFBD>generic<EFBFBD><EFBFBD> performance
registers (PMC [0]... PMC [3]). Processor implementations may provide additional
implementation-dependent PMC and PMD to increase the number of 'generic' performance
counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation
dependent. No parameter checking is performed on Index. If the Index value is
beyond the implemented PMC register range, the write is ignored.
@@ -4712,8 +4712,8 @@ AsmWritePmc (
Writes current value of Performance Monitor Data Register specified by Index.
All processor implementations provide at least 4 performance counters
(PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter overflow
status registers (PMC [0]<EFBFBD><EFBFBD> PMC [3]). Processor implementations may provide
additional implementation-dependent PMC and PMD to increase the number of <EFBFBD><EFBFBD>generic<EFBFBD><EFBFBD>
status registers (PMC [0]... PMC [3]). Processor implementations may provide
additional implementation-dependent PMC and PMD to increase the number of 'generic'
performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set
is implementation dependent. No parameter checking is performed on Index. If the
Index value is beyond the implemented PMD register range, the write is ignored.
@@ -4816,7 +4816,7 @@ AsmCpuVirtual (
as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
Status field of the PAL_CALL_RETURN structure.
This indicates that the procedure is not present in this PAL implementation.
It is the caller<EFBFBD><EFBFBD>s responsibility to check for this return code after calling
It is the caller's responsibility to check for this return code after calling
any optional PAL procedure.
No parameter checking is performed on the 5 input parameters, but there are
some common rules that the caller should follow when making a PAL call. Any