diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 85fa1f600b..15f610d82e 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
 /** @file
 
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -353,6 +353,12 @@ ArmSetTTBR0 (
   IN  VOID  *TranslationTableBase
   );
 
+VOID
+EFIAPI
+ArmSetTTBCR (
+  IN  UINT32 Bits
+  );
+
 VOID *
 EFIAPI
 ArmGetTTBR0BaseAddress (
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index fc8ea42843..74a7c177df 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -1,7 +1,7 @@
 /** @file
 *  File managing the MMU for ARMv7 architecture
 *
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2016, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -347,6 +347,17 @@ ArmConfigureMmu (
 
   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
 
+  //
+  // The TTBCR register value is undefined at reset in the Non-Secure world.
+  // Writing 0 has the effect of:
+  //   Clearing EAE: Use short descriptors, as mandated by specification.
+  //   Clearing PD0 and PD1: Translation Table Walk Disable is off.
+  //   Clearing N: Perform all translation table walks through TTBR0.
+  //               (0 is the default reset value in systems not implementing
+  //               the Security Extensions.)
+  //
+  ArmSetTTBCR (0);
+
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
                              DOMAIN_ACCESS_CONTROL_NONE(14) |
                              DOMAIN_ACCESS_CONTROL_NONE(13) |
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 085f08bfda..5d1194e7e2 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -1,7 +1,7 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
 #
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
@@ -23,6 +23,7 @@ GCC_ASM_EXPORT(ArmGetInterruptState)
 GCC_ASM_EXPORT(ArmGetFiqState)
 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
 GCC_ASM_EXPORT(ArmSetTTBR0)
+GCC_ASM_EXPORT(ArmSetTTBCR)
 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
 GCC_ASM_EXPORT(CPSRMaskInsert)
 GCC_ASM_EXPORT(CPSRRead)
@@ -111,6 +112,11 @@ ASM_PFX(ArmSetTTBR0):
   isb
   bx      lr
 
+ASM_PFX(ArmSetTTBCR):
+  mcr     p15, 0, r0, c2, c0, 2
+  isb
+  bx      lr
+
 ASM_PFX(ArmGetTTBR0BaseAddress):
   mrc     p15,0,r0,c2,c0,0
   LoadConstantToReg(0xFFFFC000, r1)
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index 228d7c8fc1..9b87b7f257 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -1,7 +1,7 @@
 //------------------------------------------------------------------------------
 //
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
 //
 // This program and the accompanying materials
 // are licensed and made available under the terms and conditions of the BSD License
@@ -85,6 +85,11 @@
   isb
   bx      lr
 
+ RVCT_ASM_EXPORT ArmSetTTBCR
+  mcr     p15, 0, r0, c2, c0, 2
+  isb
+  bx      lr
+
  RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
   mrc     p15,0,r0,c2,c0,0
   LoadConstantToReg(0xFFFFC000, r1)