diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index d64c188dc5..1a5d982022 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -238,18 +238,6 @@ ArmConfigureMmu (
 
   ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
 
-  ArmCleanInvalidateDataCache ();
-  ArmInvalidateInstructionCache ();
-
-  ArmDisableDataCache ();
-  ArmDisableInstructionCache();
-  // TLBs are also invalidated when calling ArmDisableMmu()
-  ArmDisableMmu ();
-
-  // Make sure nothing sneaked into the cache
-  ArmCleanInvalidateDataCache ();
-  ArmInvalidateInstructionCache ();
-
   // By default, mark the translation table as belonging to a uncached region
   TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
   while (MemoryTable->Length != 0) {
@@ -277,6 +265,18 @@ ArmConfigureMmu (
     return RETURN_UNSUPPORTED;
   }
 
+  ArmCleanInvalidateDataCache ();
+  ArmInvalidateInstructionCache ();
+
+  ArmDisableDataCache ();
+  ArmDisableInstructionCache();
+  // TLBs are also invalidated when calling ArmDisableMmu()
+  ArmDisableMmu ();
+
+  // Make sure nothing sneaked into the cache
+  ArmCleanInvalidateDataCache ();
+  ArmInvalidateInstructionCache ();
+
   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
     
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |