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7 Commits

Author SHA1 Message Date
Chao Li
010f7298ce OvmfPkg/RiscVVirt: Enable CpuMmio2Dxe 
CpuMmio2Dxe is supports MMIO, enable it.

Build-tested only (with "RiscVVirtQemu.dsc").

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 2024-02-06 23:51:47 +08:00
Laszlo Ersek
d7e41ce340 OvmfPkg: exclude NullMemoryTestDxe driver 
NullMemoryTestDxe was included in the OVMF platforms in historical commit
999a815e9f ("OvmfPkg: Add NullMemoryTestDxe driver", 2011-01-21). It
produces gEfiGenericMemTestProtocolGuid. With LegacyBiosDxe gone, the only
consumer of this protocol in all of edk2 is
"EmulatorPkg/Library/PlatformBmLib/PlatformBmMemoryTest.c". Thus, exclude
NullMemoryTestDxe from all OVMF platforms.

(Notably, ArmVirtPkg platforms don't include NullMemoryTestDxe either.)

Cc: Anatol Belski <anbelski@linux.microsoft.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Corvin Köhne <corvink@freebsd.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jianyong Wu <jianyong.wu@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Rebecca Cran <rebecca@bsdio.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4588
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Message-Id: <20231110235820.644381-17-lersek@redhat.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Corvin Köhne <corvink@FreeBSD.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
 2023-12-07 18:04:57 +00:00
Sunil V L
8543840cfd OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules 
Use auto alignment and FIXED FFS attribute for XIP modules similar
to [1]. Without this change, the CLANGDWARF toolchain will fail to
build with below error.

GenFfs: ERROR 1000: Unknown option
  SectionAlign option must be specified with section file.

[1] - 7669f73498

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc  Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Ard Biesheuvel <ardb@kernel.org> # Debian clang version 14.0.6
 2023-07-31 12:37:12 +00:00
Tuan Phan
33d0a3cc92 OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list 
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 2023-07-15 14:10:18 +00:00
Sunil V L
37423fa344 OvmfPkg/RiscVVirt: Add support for separate code and variable store 
Currently, RiscVVirtQemu supports unified code and variable store
mainly because only one pflash devices was available in qemu for
EDK2. However, this doesn't allow to map the code part as read-only.

With recent qemu enhancements, it is now possible for EDK2 to make
use of both pflash devices in RISC-V virt machine. So, add support
to create code and vars images separately. This also allows easy
firmware code updates without losing the variable store.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
 2023-06-23 04:49:11 +00:00
Andrei Warkentin
7fa4692636 OvmfPkg: RiscVVirt: add SATA support 
Tested with a PCIe pass-thru'd AHCI controller.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Andrei Warkentin <andrei.warkentin@intel.com>
 2023-03-08 18:10:34 +00:00
Sunil V L
92b27c2e6a OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add infrastructure files to build edk2 for RISC-V qemu virt machine.

- It follows PEI less design.
- EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW
- Leveraged from ArmVirtQemu

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
 2023-02-16 05:53:28 +00:00