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91 Commits

Author SHA1 Message Date
Michael Kinney
831d287a99 UefiCpuPkg/Include: Add VMX MSR register structures 
https://bugzilla.tianocore.org/show_bug.cgi?id=279

Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER
structures with the bit fields for these two MSRs.   Also
add MSEG_HEADER structure whose base address is in the
MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-12-01 11:58:02 -08:00
Jiewen Yao
faf2c63b4a UefiCpuPkg/Include: Add MicrocodeFlashAccessLib header. 
This library is used to abstract microcode flash region access.
This library is consumed by a microcode capsule update module.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-11-08 22:43:16 +08:00
Jiewen Yao
cc0c03874a UefiCpuPkg/Include: Add Microcode FMP definition. 
It defined ImageTypeId for Microcode.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-11-08 22:43:15 +08:00
Jeff Fan
1c8ca9a012 UefiCpuPkg/LocalApicLib: Add EFIAPI for GetProcessorLocationByApicId() 
We need to add EFIAPI for all interface service including library API.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran  <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran  <leo.duran@amd.com>
 2016-11-02 09:17:04 +08:00
Jeff Fan
262128e5ab UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation() 
GetProcessorLocation() is too generic and will conflict with the API defined in
Galileo Board Software Package v1.0.0.

This update is just to rename GetProcessorLocation() to one specific name
GetProcessorLocationByApicId().

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran  <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran  <leo.duran@amd.com>
 2016-11-02 09:16:21 +08:00
Leo Duran
73152f19c0 UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library 
1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-11-01 09:08:45 +08:00
Gary Lin
438f17665c UefiCpuPkg: Fix typos in comments 
- excute -> execute
- Retrive -> Retrieve
- possilbe -> possible
- CONTINOUS -> CONTINUOUS
- storgage -> storage
- allcated -> allocated
- triggerred -> triggered
- paramter -> parameter
- perodically -> periodically
- retore -> restore

v2:
- ruturn -> return

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-10-24 09:09:48 +08:00
Jeff Fan
d93a10c02b UefiCpuPkg/Cpuid: Remove wrong while-loop check after for-loop 
while-loop check should not co-exist with for-loop. This should be typo when we
check-in the original code. We should keep one loop only.

This issue caused CLANG38 build failure reported by
https://tianocore.acgmultimedia.com/show_bug.cgi?id=148

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
 2016-10-18 09:15:44 +08:00
Jeff Fan
ad8a2f5e68 UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:18:08 +08:00
Jeff Fan
97ea5b7ff6 UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:18:06 +08:00
Jeff Fan
b6ae7578ab UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:18:03 +08:00
Jeff Fan
eed57645e4 UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:18:01 +08:00
Jeff Fan
04e7a46528 UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:58 +08:00
Jeff Fan
94fe1b5f53 UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:56 +08:00
Jeff Fan
367f5c9c5f UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:53 +08:00
Jeff Fan
634429c0aa UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:50 +08:00
Jeff Fan
65ee84bd6b UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:47 +08:00
Jeff Fan
8bf98bd0d7 UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:45 +08:00
Jeff Fan
91e3003c97 UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:42 +08:00
Jeff Fan
c2aa191b50 UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:39 +08:00
Jeff Fan
fed6c37b4a UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:35 +08:00
Jeff Fan
e108c3f64d UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:32 +08:00
Jeff Fan
a73ab08301 UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:28 +08:00
Jeff Fan
adf109740f UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:24 +08:00
Jeff Fan
e43a671439 UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:20 +08:00
Jeff Fan
a6b7bc3c2f UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:16 +08:00
Jeff Fan
800a651d6d UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:13 +08:00
Jeff Fan
7de98828b7 UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment 
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
 2016-09-08 09:17:08 +08:00
Jeff Fan
87896d03f6 UefiCpuPkg/MpInitLib: Add MP Initialize library class definition 
MP Initialize library provides basic functionalities to do APs initialization,
to manage MP information and to wakeup APs to execute AP task.

It could be consumed by CPU MP PEI or DXE drivers to provide CPU MP PPI/Protocol
services.

v4:
  1. MpInitLibGetProcessorInfo():
     Update HealthData type from UINT32 to EFI_HEALTH_FLAGS.
     Add #include <Ppi/SecPlatformInformation.h>
  2. MpInitLibSwitchBSP():
     Return EFI_DEVICE_ERROR instead of EFI_SUCCESS if the calling processor is
     an AP.
  3. MpInitLibStartupThisAP():
     Fix several incorrect references to "APs" to match PI spec.
  4. MpInitLibSwitchBSP() and MpInitLibEnableDisableAP():
     Fix incorrect description on ProcessorNumber.
  5. Trim whitespace at end of line.

v3:
  1. Add whitespace after MpInitLibInitialize
  2. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-08-17 19:57:41 +08:00
Jeff Fan
5aa2d57667 UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM 
Add microcode definitions defined in Intel(R) 64 and IA-32 Architectures
Software Developer's Manual Volume 3A, Section 9.11.

v4:
  1. ProcessorSignature type changed to CPU_MICROCODE_PROCESSOR_SIGNATURE
  2. Add pack(1) for structure CPU_MICROCODE_HEADER and
     CPU_MICROCODE_EXTENDED_TABLE.
v3:
  1. Update SDM date to June, 2016
  2. Mention BCD format in CPU_MICROCODE_DATE
  3. Rename ProcessorChecksum to Checksum to match SDM.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-08-17 19:55:25 +08:00
Jeff Fan
a742e1865d UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions 
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

v5:
  1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-08-17 19:54:41 +08:00
Ruiyu Ni
490b048b5a UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
 2016-08-17 13:54:13 +08:00
Jeff Fan
c606a9a5b7 UefiCpuPkg/Cpuid.h: Add CPUID defines and structures for Intel SGX 
Add Intel SGX Resource Enumeration Leaves as described by Section 37.7 in
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D,
December 2015.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
 2016-03-30 08:29:49 +08:00
Michael Kinney
195c94360f UefiCpuPkg/Include: Add top level MSR include file 
Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory

Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 12:00:36 -07:00
Michael Kinney
a1e8e34d74 UefiCpuPkg/Include: Add Pentium MSR include file 
Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 12:00:19 -07:00
Michael Kinney
8e6bff8875 UefiCpuPkg/Include: Add P6 MSR include file 
Add P6 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-19.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 12:00:08 -07:00
Michael Kinney
83d4e58cb0 UefiCpuPkg/Include: Add Pentium M MSR include file 
Add Pentium M MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-18.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:59:56 -07:00
Michael Kinney
e0d87abe8f UefiCpuPkg/Include: Add Core Solo/Duo MSR include file 
Add Core Solo/Duo MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-17.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:59:44 -07:00
Michael Kinney
f4d9afde4c UefiCpuPkg/Include: Add Pentium 4 MSR include file 
Add Pentium 4 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-16.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:59:32 -07:00
Michael Kinney
3adf631660 UefiCpuPkg/Include: Add Xeon Phi MSR include file 
Add Xeon Phi MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-15.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:59:20 -07:00
Michael Kinney
6b55a245f1 UefiCpuPkg/Include: Add Skylake MSR include file 
Add Skylake MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-14.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:59:09 -07:00
Michael Kinney
54307cea18 UefiCpuPkg/Include: Add Xeon Processor D MSR include file 
Add Xeon Processor D MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-13.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:58 -07:00
Michael Kinney
d57201c0a3 UefiCpuPkg/Include: Add Broadwell MSR include file 
Add Broadwell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-12.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:47 -07:00
Michael Kinney
c67b579cd6 UefiCpuPkg/Include: Add Haswell-E MSR include file 
Add Haswell-E MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-11.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:35 -07:00
Michael Kinney
7ae88a6295 UefiCpuPkg/Include: Add Haswell MSR include file 
Add Haswell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-10.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:24 -07:00
Michael Kinney
84ada87c6b UefiCpuPkg/Include: Add Ivy Bridge MSR include file 
Add Ivy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-9.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:13 -07:00
Michael Kinney
dc5d621c60 UefiCpuPkg/Include: Add Sandy Bridge MSR include file 
Add Sandy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-8.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:58:01 -07:00
Michael Kinney
ebb74e4a3c UefiCpuPkg/Include: Add Xeon E7 MSR include file 
Add Xeon E7 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-7.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:57:40 -07:00
Michael Kinney
c5d7b07abb UefiCpuPkg/Include: Add Xeon 5600 MSR include file 
Add Xeon 5600 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-6.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:57:24 -07:00
Michael Kinney
bd946618a0 UefiCpuPkg/Include: Add Nehalem MSR include file 
Add Nehalem MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-5.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
 2016-03-13 11:57:09 -07:00