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7 Commits

Author SHA1 Message Date
Jian J Wang
2ea3576e16 IntelFrameworkModulePkg/LegacyBios: Use macro to enable/disable page 0 
Current implementation uses following two methods

    EnableNullDetection()
    DisableNullDetection()

to enable/disable page 0. These two methods will check PCD
PcdNullPointerDetectionPropertyMask to know if the page 0 is disabled or not.
This is due to the fact that old GCD service doesn't provide paging related
attributes of memory block. Since this issue has been fixed, GCD services
can be used to determine the paging status of page 0. This is also make it
possible to just use a new macro

    ACCESS_PAGE0_CODE(
      <code accessing page 0>
    );

to replace above methods to do the same job, which also makes code more
readability.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
 2017-12-08 14:38:45 +08:00
Jian J Wang
dfbfd6a4f5 IntelFrameworkModulePkg/LegacyBiosDxe: Fix GCC5 build warning 
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
 2017-10-12 10:14:58 +08:00
Jian J Wang
d057d8c4e9 IntelFrameworkModulePkg/Csm: Add code to bypass NULL pointer detection 
Legacy has to access interrupt vector, BDA, etc. located in memory between
0-4095. To allow as much code as possible to be monitored by NULL pointer
detection, we add code to temporarily disable this feature right before
those memory access and enable it again afterwards.

Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ayellet Wolman <ayellet.wolman@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
 2017-10-11 16:39:01 +08:00
li-elvin
b17f22f50b CSM should firstly set timer to enable state at first, then RestoreTpl is called. 
Signed-off-by: li-elvin
Reviewed-by: rsun3

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12555 6f19259b-4bc3-4df7-8a09-765794883524
 2011-10-21 08:45:07 +00:00
li-elvin
26a74a36c1 Use a local variable and assign 0 to it, then use it as legacy interrupt table base address. 
Signed-off-by: li-elvin
Reviewed-by: mdkinney, ydong10

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12547 6f19259b-4bc3-4df7-8a09-765794883524
 2011-10-19 00:45:13 +00:00
li-elvin
f767f99009 Update CSM module to provide the general solution when the Timer Arch Protocol is not 8254 timer. CSM module should set 8254 timer to 54ms for the execution in real mode. 
Signed-off-by: li-elvin
Reviewed-by: jyao1


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12229 6f19259b-4bc3-4df7-8a09-765794883524
 2011-08-30 05:52:28 +00:00
jljusten
bcecde140a IntelFrameworkModulePkg: Add Compatibility Support Module (CSM) drivers 
Added these drivers:
* LegacyBiosDxe
* BlockIoDxe
* KeyboardDxe
* Snp16Dxe
* VideoDxe

Signed-off-by: jljusten
Reviewed-by: mdkinney
Reviewed-by: geekboy15a

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11905 6f19259b-4bc3-4df7-8a09-765794883524
 2011-06-27 23:32:56 +00:00