141dcaed6c
UefiCpuPkg: Add cache operations support for Arch proto
...
With CMO operations available for RISC-V, utilize them in CPU
Architecture protocol.
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com >
Cc: Gerd Hoffmann <kraxel@redhat.com >
Cc: Laszlo Ersek <lersek@redhat.com >
Cc: Rahul Kumar <rahul1.kumar@intel.com >
Cc: Ray Ni <ray.ni@intel.com >
Cc: Sunil VL <sunilvl@ventanamicro.com >
Cc: Andrei Warkentin <andrei.warkentin@intel.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2024-02-04 03:09:12 +00:00
f220dcbba8
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
...
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com >
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2023-07-15 14:10:18 +00:00
089013a697
UefiCpuPkg: Update code to be more C11 compliant by using __func__
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__FUNCTION__ is a pre-standard extension that gcc and Visual C++ among
others support, while __func__ was standardized in C99.
Since it's more standard, replace __FUNCTION__ with __func__ throughout
UefiCpuPkg.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com >
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com >
Reviewed-by: Ard Biesheuvel <ardb@kernel.org >
Reviewed-by: Ray Ni <ray.ni@intel.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2023-04-10 14:19:57 +00:00
c27cdc941d
UefiCpuPkg: Add CpuDxeRiscV64 module
...
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
This is copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe
and added the RISCV_EFI_BOOT_PROTOCOL support.
Cc: Eric Dong <eric.dong@intel.com >
Cc: Ray Ni <ray.ni@intel.com >
Cc: Rahul Kumar <rahul1.kumar@intel.com >
Cc: Daniel Schaefer <git@danielschaefer.me >
Cc: Gerd Hoffmann <kraxel@redhat.com >
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com >
Acked-by: Abner Chang <abner.chang@amd.com >
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com >
2023-02-16 05:53:28 +00:00
