3 Commits

Author	SHA1	Message	Date
Jian J Wang	16b918bbaf	UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler ... Once the #PF handler has set the page to be 'present', there should be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used for this purpose. 'TF' bit will be set in interrupted function context so that it can be triggered once the cpu control returns back to the instruction causing #PF and re-execute it. This is an necessary step to implement non-stop mode for Heap Guard and NULL Pointer Detection feature. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>	2018-08-30 07:22:29 +08:00
Liming Gao	2db0ccc2d7	UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain ... https://bugzilla.tianocore.org/show_bug.cgi?id=849 In V2, use mov rax, strict qword 0 to replace the hard code db. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>	2018-01-16 23:42:48 +08:00
Liming Gao	fb501e33c3	UefiCpuPkg CpuExceptionHandlerLib:Convert X64/ExceptionHandlerAsm.asm to NASM ... The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert X64/ExceptionHandlerAsm.asm to X64/ExceptionHandlerAsm.nasm. Then, manually update nasm to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>	2016-06-28 09:52:10 +08:00