1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=180
The PCI_SEGMENT_LIB_ADDRESS() macro puts the Segment number
into bits 32..47 of the logical address that is returned.
The portable method to put Segment in this bit range is to
use LShitU64(). For 64-bit CPUs, this is optimized well
by the compiler. For 32-bit CPUs, a call to LSHiftU64()
is included in the generated binaries. However, if the
Segment parameter is 0, then no shift is required. Add
a check for Segment set to 0 and provide an optimized
macro implementation that does not call LShiftU64().
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class.
3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524
2. Added assert() for AsmFxRestore() in x86LowLevel.c of BaseLib
3. Added assert() for LongJump() in LongJump.c of BaseLib
4. Changed parameter type of Value from "IN" to "IN OUT" for InterLockedComparedExchanged32/64/pointer() functions to sync with MWG-0.55a
5. Changed functions header of all BitField functions of BaseLib, BaseIoLibIntrinsic, BasePciCf8Lib, BasePciExpressLib, BasePciLibCf8, BasePciLibPciExpressLib DxeIoLibCpuIo, PeiIoLibCpuIo etc, to follow MWG-0.55a.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@565 6f19259b-4bc3-4df7-8a09-765794883524
