sravan/system76-edk2
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8 Commits

Author SHA1 Message Date
Olivier Martin
f3c5066fa6 ArmPkg/AArch64.h: Added Exception Syndrome Register definitions 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15709 6f19259b-4bc3-4df7-8a09-765794883524
 2014-07-29 14:09:10 +00:00
Olivier Martin
6a44c22732 ArmPkg/AArch64: Added ARM_HCR_TSC definition 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15708 6f19259b-4bc3-4df7-8a09-765794883524
 2014-07-29 14:08:15 +00:00
Olivier Martin
7e119c677e ArmPkg/AArch64.h: Added SPSR and Timer register definitions 
These timer register definitions are AArch64 specific. It is the reason
why they are into this file and not into Chipset/ArmArchTimer.h.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15706 6f19259b-4bc3-4df7-8a09-765794883524
 2014-07-29 14:06:33 +00:00
Olivier Martin
27331bff97 ArmPkg: Added new ARM Processor Feature Register definitions 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
 2014-06-03 16:39:23 +00:00
Olivier Martin
b7dd4dbd26 ArmPkg/Chipset: Added ARMv8 CPU's PartNum 
PartNum is the field of MIDR that returns the CPU name.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15395 6f19259b-4bc3-4df7-8a09-765794883524
 2014-03-26 19:29:31 +00:00
Olivier Martin
168d724568 ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLib 
These functions are not chipset specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
 2013-11-28 21:37:36 +00:00
Olivier Martin
d6dc67ba1b ARM: Remove NSACR from the common code 
NSACR (Non-Secure Access Control Register) is AArch32 specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
 2013-08-06 10:59:19 +00:00
Harry Liebel
25402f5d06 ArmPkg: Added Aarch64 support 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
 2013-07-18 18:07:46 +00:00