3d5352d934
UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
...
The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
supported when Svpbmt extension available.
Cc: Gerd Hoffmann <kraxel@redhat.com >
Cc: Laszlo Ersek <lersek@redhat.com >
Cc: Rahul Kumar <rahul1.kumar@intel.com >
Cc: Ray Ni <ray.ni@intel.com >
Signed-off-by: Tuan Phan <tphan@ventanamicro.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2024-04-08 05:43:59 +00:00
6ddfbeb0d6
UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTN
...
While UINTN defined for RISC-V 64 bits is UINT64, explictly using UINT64
for those variables that clearly are UINT64.
Cc: Gerd Hoffmann <kraxel@redhat.com >
Cc: Laszlo Ersek <lersek@redhat.com >
Cc: Rahul Kumar <rahul1.kumar@intel.com >
Cc: Ray Ni <ray.ni@intel.com >
Signed-off-by: Tuan Phan <tphan@ventanamicro.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2024-04-08 05:43:59 +00:00
772ec92577
UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
...
Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com >
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com >
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2023-10-17 07:44:25 +00:00
f220dcbba8
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
...
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com >
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com >
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com >
2023-07-15 14:10:18 +00:00
