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Author SHA1 Message Date
Bob Feng
c4663e7277 pip-requirement: Upgrade the edk2-basetools version from 0.1.29 to 0.1.39 
features and bug fixes:
1. Revert "BaseTools: Fix DSC LibraryClass precedence rule"
2. BaseTools: Correct BPDG tool error prints
3. BaseTools: Remove duplicated words in Python tools
4. BaseTools/FMMT: Add Extract FV function
5. BaseTools/FMMT: Add Shrink Fv function
6. BaseTools: Add support for SUBTYPE_GUID section generation
7. BaseTools: Support COMPAT16 section generation
8. BaseTools/GenFds: Correct file type set for the PIC section
9. BaseTools: Correct initialization data size check for array PCDs
10. BaseTools: Add missing spaces for PCD expression values in AutoGenC

Signed-off-by: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Yuwei Chen <yuwei.chen@intel.com>
 2022-10-19 04:33:25 +00:00
Jason Lou
9d6915ca91 UefiCpuPkg/Test: Add unit tests for MP service PPI and Protocol 
The code changes add unit tests based on current UnitTestFramework.
EdkiiPeiMpServices2PpiPeiUnitTest PEI module is used to test
EdkiiPeiMpServices2Ppi and EfiMpServiceProtocolDxeUnitTest DXE driver is
used to test EfiMpServiceProtocol.

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Tan, Dun
6f1bb567aa UefiCpuPkg: Add R8/R9 etc in EccCheck ExceptionList 
Add GENERAL_REGISTER.R8/R9 etc in EccCheck ExceptionList
of UefiCpuPkg/UefiCpuPkg.ci.yaml to pass CI EccCheck.R8/R9
in structure GENERAL_REGISTER of CpuExceptionHandlerTest.h
lead to EccCheck failure since no lower case characters in
R8/R9/R10 etc.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Tan, Dun
012e424601 UefiCpuPkg: Add Pei/DxeCpuExceptionHandlerLibUnitTest in dsc 
Add Pei/DxeCpuExceptionHandlerLibUnitTest module in UefiCpuPkg.dsc

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Tan, Dun
055eaacc34 UefiCpuPkg: Add Unit tests for PeiCpuExceptionHandlerLib 
The previous change adds unit test for DxeCpuExeptionHandlerLib
in 64bit mode. This change create a PEIM to add unit test for
PeiCpuExceptionHandlerLib based on previous change.It can run
in both 32bit and 64bit modes.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Tan, Dun
beabde5875 UefiCpuPkg: Add Unit tests for DxeCpuExceptionHandlerLib 
Add target based unit tests for the DxeCpuExceptionHandlerLib.
A DXE driver is created to test DxeCpuExceptionHandlerLib.

Four test cases are created in this Unit Test module:
a.Test if exception handler can be registered/unregistered
for no error code exception.In the test case, only no error
code exception is triggered and tested by INTn instruction.

b.Test if exception handler can be registered/unregistered
for GP and PF. In the test case, GP exception is triggered
and tested by setting CR4_RESERVED_BIT to 1. PF exception
is triggered by writting to not-present or RO address.

c.Test if CpuContext is consistent before and after exception.
In this test case:
1.Set Cpu register to mExpectedContextInHandler before
exception. 2.Trigger exception specified by ExceptionType.
3.Store SystemContext in mActualContextInHandler and set
SystemContext to mExpectedContextAfterException in handler.
4.After return from exception, store Cpu registers in
mActualContextAfterException.
The expectation is:
1.Register values in mActualContextInHandler are the same
with register values in mExpectedContextInHandler.
2.Register values in mActualContextAfterException are the
same with register values mActualContextAfterException.

d.Test if stack overflow can be captured by CpuStackGuard
in both Bsp and AP. In this test case, stack overflow is
triggered by a funtion which calls itself continuously.
This test case triggers stack overflow in both BSP and AP.
All AP use same Idt with Bsp. The expectation is:
1. PF exception is triggered (leading to a DF if sepereated
stack is not prepared for PF) when Rsp<=StackBase+SIZE_4KB
since [StackBase, StackBase + SIZE_4KB] is marked as not
present in page table when PcdCpuStackGuard is TRUE.
2. Stack for PF/DF exception handler in both Bsp and AP is
succussfully switched by InitializeSeparateExceptionStacks.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Tan, Dun
b8e54e15de UefiCpuPkg/CpuPageTableLib:Support PAE paging for PageTableParse 
Support PAE paging for PageTableParse API in CpuPageTableLib.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Liu, Zhiguang
a7e070808c UefiCpuPkg:Add RegisterExceptionHandler in PeiCpuExceptionHandlerLib 
The PEI instance of the CpuExceptionHandlerLib didn't implement the
RegisterCpuInterruptHandler() API. This patch adds the missing API.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
 2022-10-17 08:03:06 +00:00
Pierre Gondois
d618fe05bf BaseTools: Remove duplicated words in C tools 
In an effort to clean the documentation of the above
package, remove duplicated words.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
 2022-10-16 04:21:29 +00:00
Foster Nong
8fc06b6e19 Fix bug on SRIOV ReservedBusNum when ARI enable. 
If a device which support both features SR-IOV/ARI  has multi
functions, which maybe support 8-255. After enable ARI forwarding in
the root port and ARI Capable Hierarchy in the SR-IOV PF0.
The device will support and expose multi functions(0-255) with ARI ID routing.
In next device loop in below for() code, actually it still be in the
same SR-IOV device, and just some PF which is over 8 or higher
one(n*8), PciAllocateBusNumber() will allocate bus
number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset
TempReservedBusNum as 0 in this case,it will allocate wrong bus number
for this PF because TempReservedBusNum should be total previous PF's
reserved bus numbers.

code:
  for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
    TempReservedBusNum = 0;
    for (Func = 0; Func <= PCI_MAX_FUNC; Func++) {
    //
    // Check to see whether a pci device is present
    //
    Status = PciDevicePresent (
                 PciRootBridgeIo,
                 &Pci,
                 StartBusNumber,
                 Device,
                 Func
                 );
    ...
    Status = PciAllocateBusNumber (PciDevice, *SubBusNumber,
    (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber);

The solution is add a new flag IsAriEnabled to help handle this case.
if ARI is enabled, then TempReservedBusNum will not be reset again
during all functions(1-255) scan with checking flag IsAriEnabled.

Signed-off-by: Foster Nong <foster.nong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
 2022-10-14 07:07:01 +00:00
Foster Nong
4aa7e66c06 MdeModulePkg: Fixed extra 1 SR-IOV reserved bus 
Below code will calculate the reserved bus number for the each PF.

Based on the VF routing ID algorithm, PFRid and LastVF in below code
already sure that "All VFs and PFs must have distinct Routing IDs".
PF will be assigned Routing ID based on secBusNumber, ReservedBusNum
will add into SubBusNumber directly. So the SR-IOV device will be
assigned bus range as SecBusNumber ~ (SubBusNumber=(SecBusNumber +
ReservedBusNum)).
Thus "+1" in below code will cause extra 1 bus, and introduce a bus hole.

 PFRid  = EFI_PCI_RID (Bus, Device, Func);
 LastVF = PFRid + FirstVFOffset + (PciIoDevice->InitialVFs - 1) * VFStride;
 PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
 Bus + 1);

In SR-IOV spec, there is a note in section 2.1.2:
Note: Bus Numbers are a constrained resource. Devices are strongly
encouraged to avoid leaving ?holes? in their Bus Number usage to avoid
wasting Bus Numbers

So the issue can be fixed with below code change.
  PciIoDevice->ReservedBusNum = (UINT16)(EFI_PCI_BUS_OF_RID (LastVF) -
  Bus);

https://bugzilla.tianocore.org/show_bug.cgi?id=4069

Signed-off-by: Foster Nong <foster.nong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
 2022-10-14 07:07:01 +00:00
Chao Li
e0200cc47a NetworkPkg: Add LoongArch64 architecture. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 architecture in to NetworkPkg.

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
2ce4bfb843 MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Implement LoongArch DxeIPL instance.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Guomin Jiang <guomin.jiang@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
380821a949 MdeModulePkg/CapsuleRuntimeDxe: Add LoongArch64 architecture. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch in INF for building CapsuleRuntimeDxe LoongArch64 image.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Guomin Jiang <guomin.jiang@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
dad7fc29d9 MdeModulePkg/Logo: Add LoongArch64 architecture. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 architecture to the Logo.

Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
ced203c3d5 MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for BaseSafeIntLib. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 architecture for BaseSafeIntLib library.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
104df6136f MdePkg/BaseSynchronizationLib: LoongArch cache related code. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Support LoongArch cache related functions.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
f89815a125 MdePkg/BaseCpuLib: LoongArch Base CPU library implementation. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Implement LoongArch CPU related functions in BaseCpuLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
dbbb045ff1 MdePkg/BasePeCoff: Add LoongArch PE/Coff related code. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch image relocation.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
10d291f746 MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

LoongArch MMIO library instance, use the IoLibNoIo.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
264e930de0 MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Implement LoongArch cache maintenance functions in
BaseCacheMaintenanceLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
cd24eb578b MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch LOONGARCH64 BaseLib functions.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
f0a704f9b5 MdePkg/Include: LoongArch definitions. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch processor related definitions.

For the Http boot and PXE boot types seeing this URL section "Processor
Architecture Type" for the LOONGARCH values:
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml

For definitions of PE/COFF and LOONGARCH relocation types, see the
"Machine Types" and "Basic Relocation Types" sections of this URL for
LOONGARCH values:
https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

For the register definitions of exceptions context, see the UEFI V2.10
18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH
definitions:
https://uefi.org/specs/UEFI/2.10/18_Protocols_Debugger_Support.html

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
76bf716a7a MdePkg: Add LoongArch LOONGARCH64 binding 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 sections in MdePkg.dec and LOONGARCH64 ProcessorBind.h

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
b1b5177a0c .pytool: Add LoongArch64 architecture on LoongArch64 EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 architecture on LoongArch64 EDK2 CI testing.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
ab9768cd46 .azurepipelines: Add LoongArch64 architecture on LoongArch64 EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 architecture on LoongArch64 EDK2 CI.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
bcdafe1179 BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

EDK CI for LoongArch64 architecture

Enable LoongArch64 architecture for LoongArch64 EDK2 CI testing.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
114e6075b6 BaseTools: Add LoongArch64 binding. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LoongArch64 ProcessorBin.h and add LoongArch to Makefiles.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
c53807cb7b BaseTools: Updated build tools to support new LoongArch. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Python code changes for building EDK2 LoongArch platform.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
cb4f1dfcc1 BaseTools: Updated for GCC5 tool chain for LoongArch platfrom. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

BaseTools define template files changes for building EDK2 LoongArch
platform.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
1aa311d175 BaseTools: Update GenFw/GenFv to support LoongArch platform. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

C code changes for building EDK2 LoongArch platform.

For definitions of PE/COFF and LOONGARCH relocation types, see the
"Machine Types" and "Basic Relocation Types" sections of this URL for
LOONGARCH values:
https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Co-authored-by: Yang Zhou <zhouyang@loongson.cn>
Co-authored-by: Xiaotian Wu <wuxiaotian@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
082b563fc4 .python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add Loongson and LOONGARCH to "words" section in cspell.base.yaml file
to avoid spelling check error.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
10daf3ee24 MdeModulePkg: Use LockBoxNullLib for LOONGARCH64 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

LoongArch doesn't have SMM by now.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
23d873f4cf MdePkg/DxeServicesLib: Add LOONGARCH64 architecture 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture to MdePkg/DxeServiceLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
6e1ddbab8d UnitTestFrameworkPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture to UnitTestFramworkPkg for LOONGARCH64 EDK2
CI.

Cc: Michael D Kinney <michael.d.kinney@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
78b081334e ShellPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture to ShellPkg for EDK2 CI testing.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
711ee4103a SecurityPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture to SecurityPkg for EDK2 CI testing.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
d2c0d52ed6 MdePkg/Include: Add LOONGARCH related definitions EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI.

For the LOONGARCH values, please seeing following URL section
"Processor Architecture Types":
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
c5f4b4fd03 CryptoPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
ee2ea7868a NetworkPkg/HttpBootDxe: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH architecture for EDK2 CI testing.

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
ad8f2b7251 NetworkPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
2067672ded FmpDevicePkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
d8c073c89b FatPkg: Add LOONGARCH64 architecture for EDK2 CI. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Ray Ni <ray.ni@intel.com>

Signed-off-by: Chao Li  <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
 2022-10-14 02:16:33 +00:00
Chao Li
e25963d458 MdePkg: Added LoongArch jump buffer register definition to MdePkg.ci.yaml 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

If the new Arch register is defined in BaseLib.h when running
the CI tests, it will give an ECC check error. Add the
LoongArch register defined in the ExceptionList field to make
the CI ECC check pass.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Chao Li
0371178d0b MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

DebugSupport.h is all defined by UEFI Spec, most of the code
doesn't fit EDKII coding style, add it to IgnoreFiles field to
make CI ECC check pass.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
 2022-10-14 02:16:33 +00:00
Gua Guo
5bd2dbc698 UefiPayloadPkg: Remove deprecate Crypto Service 
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4096

TDES and ARC4 services are deprecated so set it as disable.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: James Lu <james.lu@intel.com>
Signed-off-by: Gua Guo <gua.guo@intel.com>
 2022-10-13 10:43:52 +08:00
Qi Zhang
e7d7f02c8e CryptoPkg: add Unit Test for X509 new function. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4082

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
 2022-10-12 06:38:15 +00:00
Qi Zhang
22745df666 CryptoPkg: add new X509 function to Crypto Service. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4082

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
 2022-10-12 06:38:15 +00:00
Qi Zhang
8ecae3d641 CryptoPkg: add new X509 function. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4082

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
 2022-10-12 06:38:15 +00:00
Qi Zhang
190f77f8f4 CryptoPkg: add new X509 function definition. 
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4082

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Qi Zhang <qi1.zhang@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
 2022-10-12 06:38:15 +00:00