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1450 Commits
intel-fsp-
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edk2-stabl
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|
b1d3895fb9 |
@@ -7,8 +7,10 @@
|
|||||||
##
|
##
|
||||||
trigger:
|
trigger:
|
||||||
- master
|
- master
|
||||||
|
- stable/*
|
||||||
pr:
|
pr:
|
||||||
- master
|
- master
|
||||||
|
- stable/*
|
||||||
|
|
||||||
jobs:
|
jobs:
|
||||||
- template: templates/pr-gate-build-job.yml
|
- template: templates/pr-gate-build-job.yml
|
||||||
|
@@ -5,7 +5,7 @@
|
|||||||
# NOTE: This example monitors pull requests against the edk2-ci branch. Most
|
# NOTE: This example monitors pull requests against the edk2-ci branch. Most
|
||||||
# environments would replace 'edk2-ci' with 'master'.
|
# environments would replace 'edk2-ci' with 'master'.
|
||||||
#
|
#
|
||||||
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
# https://github.com/tianocore
|
# https://github.com/tianocore
|
||||||
@@ -16,6 +16,7 @@ trigger: none
|
|||||||
|
|
||||||
pr:
|
pr:
|
||||||
- master
|
- master
|
||||||
|
- stable/*
|
||||||
|
|
||||||
pool:
|
pool:
|
||||||
vmImage: 'ubuntu-latest'
|
vmImage: 'ubuntu-latest'
|
||||||
|
@@ -6,9 +6,11 @@
|
|||||||
##
|
##
|
||||||
trigger:
|
trigger:
|
||||||
- master
|
- master
|
||||||
|
- stable/*
|
||||||
|
|
||||||
pr:
|
pr:
|
||||||
- master
|
- master
|
||||||
|
- stable/*
|
||||||
|
|
||||||
jobs:
|
jobs:
|
||||||
- template: templates/pr-gate-build-job.yml
|
- template: templates/pr-gate-build-job.yml
|
||||||
|
@@ -51,6 +51,12 @@ steps:
|
|||||||
# Set default
|
# Set default
|
||||||
- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
|
- bash: echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
|
||||||
|
|
||||||
|
# Fetch the target branch so that pr_eval can diff them.
|
||||||
|
# Seems like azure pipelines/github changed checkout process in nov 2020.
|
||||||
|
- script: git fetch origin $(System.PullRequest.targetBranch)
|
||||||
|
displayName: fetch target branch
|
||||||
|
condition: eq(variables['Build.Reason'], 'PullRequest')
|
||||||
|
|
||||||
# trim the package list if this is a PR
|
# trim the package list if this is a PR
|
||||||
- task: CmdLine@1
|
- task: CmdLine@1
|
||||||
displayName: Check if ${{ parameters.build_pkg }} need testing
|
displayName: Check if ${{ parameters.build_pkg }} need testing
|
||||||
|
@@ -4,6 +4,7 @@
|
|||||||
# template file used to build supported packages.
|
# template file used to build supported packages.
|
||||||
#
|
#
|
||||||
# Copyright (c) Microsoft Corporation.
|
# Copyright (c) Microsoft Corporation.
|
||||||
|
# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
##
|
##
|
||||||
|
|
||||||
@@ -20,6 +21,9 @@ jobs:
|
|||||||
#Use matrix to speed up the build process
|
#Use matrix to speed up the build process
|
||||||
strategy:
|
strategy:
|
||||||
matrix:
|
matrix:
|
||||||
|
TARGET_ARM_ARMPLATFORM:
|
||||||
|
Build.Pkgs: 'ArmPkg,ArmPlatformPkg'
|
||||||
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
||||||
TARGET_MDE_CPU:
|
TARGET_MDE_CPU:
|
||||||
Build.Pkgs: 'MdePkg,UefiCpuPkg'
|
Build.Pkgs: 'MdePkg,UefiCpuPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
||||||
@@ -30,17 +34,17 @@ jobs:
|
|||||||
Build.Pkgs: 'MdeModulePkg'
|
Build.Pkgs: 'MdeModulePkg'
|
||||||
Build.Targets: 'RELEASE,NO-TARGET'
|
Build.Targets: 'RELEASE,NO-TARGET'
|
||||||
TARGET_NETWORK:
|
TARGET_NETWORK:
|
||||||
Build.Pkgs: 'NetworkPkg'
|
Build.Pkgs: 'NetworkPkg,RedfishPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
||||||
TARGET_OTHER:
|
TARGET_OTHER:
|
||||||
Build.Pkgs: 'PcAtChipsetPkg,ShellPkg'
|
Build.Pkgs: 'PcAtChipsetPkg,ShellPkg,StandaloneMmPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
||||||
TARGET_FMP_FAT_TEST:
|
TARGET_FMP_FAT_TEST:
|
||||||
Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg'
|
Build.Pkgs: 'FmpDevicePkg,FatPkg,UnitTestFrameworkPkg,DynamicTablesPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
||||||
TARGET_CRYPTO:
|
TARGET_CRYPTO:
|
||||||
Build.Pkgs: 'CryptoPkg'
|
Build.Pkgs: 'CryptoPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET,NOOPT'
|
||||||
TARGET_SECURITY:
|
TARGET_SECURITY:
|
||||||
Build.Pkgs: 'SecurityPkg'
|
Build.Pkgs: 'SecurityPkg'
|
||||||
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
Build.Targets: 'DEBUG,RELEASE,NO-TARGET'
|
||||||
@@ -63,23 +67,3 @@ jobs:
|
|||||||
build_pkgs: $(Build.Pkgs)
|
build_pkgs: $(Build.Pkgs)
|
||||||
build_targets: $(Build.Targets)
|
build_targets: $(Build.Targets)
|
||||||
build_archs: ${{ parameters.arch_list }}
|
build_archs: ${{ parameters.arch_list }}
|
||||||
|
|
||||||
- job: FINISHED
|
|
||||||
dependsOn: Build_${{ parameters.tool_chain_tag }}
|
|
||||||
condition: succeeded()
|
|
||||||
steps:
|
|
||||||
- checkout: none
|
|
||||||
- script: |
|
|
||||||
echo FINISHED
|
|
||||||
sleep 10
|
|
||||||
displayName: FINISHED
|
|
||||||
|
|
||||||
- job: FAILED
|
|
||||||
dependsOn: Build_${{ parameters.tool_chain_tag }}
|
|
||||||
condition: failed()
|
|
||||||
steps:
|
|
||||||
- checkout: none
|
|
||||||
- script: |
|
|
||||||
echo FAILED
|
|
||||||
sleep 10
|
|
||||||
displayName: FAILED
|
|
||||||
|
@@ -31,6 +31,12 @@ steps:
|
|||||||
echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
|
echo "##vso[task.setvariable variable=pkgs_to_build]${{ parameters.build_pkgs }}"
|
||||||
echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
|
echo "##vso[task.setvariable variable=pkg_count]${{ 1 }}"
|
||||||
|
|
||||||
|
# Fetch the target branch so that pr_eval can diff them.
|
||||||
|
# Seems like azure pipelines/github changed checkout process in nov 2020.
|
||||||
|
- script: git fetch origin $(System.PullRequest.targetBranch)
|
||||||
|
displayName: fetch target branch
|
||||||
|
condition: eq(variables['Build.Reason'], 'PullRequest')
|
||||||
|
|
||||||
# trim the package list if this is a PR
|
# trim the package list if this is a PR
|
||||||
- task: CmdLine@1
|
- task: CmdLine@1
|
||||||
displayName: Check if ${{ parameters.build_pkgs }} need testing
|
displayName: Check if ${{ parameters.build_pkgs }} need testing
|
||||||
|
@@ -13,7 +13,7 @@ parameters:
|
|||||||
steps:
|
steps:
|
||||||
- task: NodeTool@0
|
- task: NodeTool@0
|
||||||
inputs:
|
inputs:
|
||||||
versionSpec: '10.x'
|
versionSpec: '14.x'
|
||||||
#checkLatest: false # Optional
|
#checkLatest: false # Optional
|
||||||
condition: and(gt(variables.pkg_count, 0), succeeded())
|
condition: and(gt(variables.pkg_count, 0), succeeded())
|
||||||
|
|
||||||
|
5
.gitmodules
vendored
5
.gitmodules
vendored
@@ -6,7 +6,7 @@
|
|||||||
url = https://github.com/ucb-bar/berkeley-softfloat-3.git
|
url = https://github.com/ucb-bar/berkeley-softfloat-3.git
|
||||||
[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
|
[submodule "UnitTestFrameworkPkg/Library/CmockaLib/cmocka"]
|
||||||
path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
|
path = UnitTestFrameworkPkg/Library/CmockaLib/cmocka
|
||||||
url = https://git.cryptomilk.org/projects/cmocka.git
|
url = https://github.com/tianocore/edk2-cmocka.git
|
||||||
[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
|
[submodule "MdeModulePkg/Universal/RegularExpressionDxe/oniguruma"]
|
||||||
path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
|
path = MdeModulePkg/Universal/RegularExpressionDxe/oniguruma
|
||||||
url = https://github.com/kkos/oniguruma
|
url = https://github.com/kkos/oniguruma
|
||||||
@@ -17,3 +17,6 @@
|
|||||||
path = BaseTools/Source/C/BrotliCompress/brotli
|
path = BaseTools/Source/C/BrotliCompress/brotli
|
||||||
url = https://github.com/google/brotli
|
url = https://github.com/google/brotli
|
||||||
ignore = untracked
|
ignore = untracked
|
||||||
|
[submodule "RedfishPkg/Library/JsonLib/jansson"]
|
||||||
|
path = RedfishPkg/Library/JsonLib/jansson
|
||||||
|
url = https://github.com/akheron/jansson
|
||||||
|
8
.mailmap
8
.mailmap
@@ -38,6 +38,7 @@ Jim Dailey <Jim.Dailey@Dell.com>
|
|||||||
Jim Dailey <Jim.Dailey@Dell.com> <Jim_Dailey@Dell.com>
|
Jim Dailey <Jim.Dailey@Dell.com> <Jim_Dailey@Dell.com>
|
||||||
Laszlo Ersek <lersek@redhat.com> <lersek@6f19259b-4bc3-4df7-8a09-765794883524>
|
Laszlo Ersek <lersek@redhat.com> <lersek@6f19259b-4bc3-4df7-8a09-765794883524>
|
||||||
Laszlo Ersek <lersek@redhat.com> <lersek@Edk2>
|
Laszlo Ersek <lersek@redhat.com> <lersek@Edk2>
|
||||||
|
Liming Gao <gaoliming@byosoft.com.cn>
|
||||||
Liming Gao <liming.gao@intel.com> <Gao, Liming liming.gao@intel.com>
|
Liming Gao <liming.gao@intel.com> <Gao, Liming liming.gao@intel.com>
|
||||||
Liming Gao <liming.gao@intel.com> <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>
|
Liming Gao <liming.gao@intel.com> <lgao4@6f19259b-4bc3-4df7-8a09-765794883524>
|
||||||
Liming Gao <liming.gao@intel.com> <lgao4@Edk2>
|
Liming Gao <liming.gao@intel.com> <lgao4@Edk2>
|
||||||
@@ -47,6 +48,7 @@ Marc-André Lureau <marcandre.lureau@redhat.com> <marcandre.lureau@redhat.com>
|
|||||||
Marvin Häuser <Marvin.Haeuser@outlook.com>
|
Marvin Häuser <Marvin.Haeuser@outlook.com>
|
||||||
Marvin Häuser <Marvin.Haeuser@outlook.com> edk2-devel <edk2-devel-bounces@lists.01.org>
|
Marvin Häuser <Marvin.Haeuser@outlook.com> edk2-devel <edk2-devel-bounces@lists.01.org>
|
||||||
Marvin Häuser <mhaeuser@outlook.de>
|
Marvin Häuser <mhaeuser@outlook.de>
|
||||||
|
Matt DeVillier <matt.devillier@gmail.com>
|
||||||
Maurice Ma <maurice.ma@intel.com>
|
Maurice Ma <maurice.ma@intel.com>
|
||||||
Michael Kubacki <michael.a.kubacki@intel.com>
|
Michael Kubacki <michael.a.kubacki@intel.com>
|
||||||
Michael Kubacki <michael.a.kubacki@intel.com> </o=Intel/ou=External (FYDIBOHF25SPDLT)/cn=Recipients/cn=3c8b0226e75f4ab08d20c151cb7a8a72>
|
Michael Kubacki <michael.a.kubacki@intel.com> </o=Intel/ou=External (FYDIBOHF25SPDLT)/cn=Recipients/cn=3c8b0226e75f4ab08d20c151cb7a8a72>
|
||||||
@@ -60,14 +62,20 @@ Ray Ni <ray.ni@intel.com> <niruiyu@Edk2>
|
|||||||
Ray Ni <ray.ni@intel.com> <ruiyu.ni@intel.com>
|
Ray Ni <ray.ni@intel.com> <ruiyu.ni@intel.com>
|
||||||
Ray Ni <ray.ni@intel.com> <Ruiyu.ni@Intel.com>
|
Ray Ni <ray.ni@intel.com> <Ruiyu.ni@Intel.com>
|
||||||
Ray Ni <ray.ni@intel.com> <ruyu.ni@intel.com>
|
Ray Ni <ray.ni@intel.com> <ruyu.ni@intel.com>
|
||||||
|
Rebecca Cran <rebecca@bluestop.org>
|
||||||
|
Rebecca Cran <rebecca@bsdio.com>
|
||||||
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <elhaj@hpe.com>
|
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <elhaj@hpe.com>
|
||||||
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <Samer El-Haj-Mahmoud elhaj@hp.com>
|
Samer El-Haj-Mahmoud <samer@elhajmahmoud.com> <Samer El-Haj-Mahmoud elhaj@hp.com>
|
||||||
Shenglei Zhang <shenglei.zhang@intel.com>
|
Shenglei Zhang <shenglei.zhang@intel.com>
|
||||||
Star Zeng <star.zeng@intel.com>
|
Star Zeng <star.zeng@intel.com>
|
||||||
Star Zeng <star.zeng@intel.com> <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524>
|
Star Zeng <star.zeng@intel.com> <lzeng14@6f19259b-4bc3-4df7-8a09-765794883524>
|
||||||
Star Zeng <star.zeng@intel.com> <lzeng14@Edk2>
|
Star Zeng <star.zeng@intel.com> <lzeng14@Edk2>
|
||||||
|
Tom Lendacky <thomas.lendacky@amd.com>
|
||||||
Vitaly Cheptsov <vit9696@protonmail.com> Vitaly Cheptsov via Groups.Io <vit9696=protonmail.com@groups.io>
|
Vitaly Cheptsov <vit9696@protonmail.com> Vitaly Cheptsov via Groups.Io <vit9696=protonmail.com@groups.io>
|
||||||
Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Vladimir Olovyannikov via edk2-devel <edk2-devel@lists.01.org>
|
Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Vladimir Olovyannikov via edk2-devel <edk2-devel@lists.01.org>
|
||||||
|
Wei6 Xu <wei6.xu@intel.com>
|
||||||
Yonghong Zhu <yonghong.zhu@intel.com>
|
Yonghong Zhu <yonghong.zhu@intel.com>
|
||||||
Yonghong Zhu <yonghong.zhu@intel.com> <yzhu52@Edk2>
|
Yonghong Zhu <yonghong.zhu@intel.com> <yzhu52@Edk2>
|
||||||
Yu-Chen Lin <yuchenlin@synology.com>
|
Yu-Chen Lin <yuchenlin@synology.com>
|
||||||
|
Zhichao Gao <zhichao.gao@intel.com>
|
||||||
|
Zhiguang Liu <zhiguang.liu@intel.com>
|
||||||
|
@@ -16,7 +16,7 @@
|
|||||||
# * This file must be checked into the 'default' branch of a repo. Copies
|
# * This file must be checked into the 'default' branch of a repo. Copies
|
||||||
# of this file on other branches of a repo are ignored by Mergify.
|
# of this file on other branches of a repo are ignored by Mergify.
|
||||||
#
|
#
|
||||||
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
# https://github.com/apps/mergify
|
# https://github.com/apps/mergify
|
||||||
@@ -24,74 +24,27 @@
|
|||||||
#
|
#
|
||||||
##
|
##
|
||||||
|
|
||||||
pull_request_rules:
|
queue_rules:
|
||||||
|
- name: default
|
||||||
|
conditions:
|
||||||
|
- base~=(^main|^master|^stable/)
|
||||||
|
- label=push
|
||||||
|
|
||||||
|
pull_request_rules:
|
||||||
- name: Automatically merge a PR when all required checks pass and 'push' label is present
|
- name: Automatically merge a PR when all required checks pass and 'push' label is present
|
||||||
conditions:
|
conditions:
|
||||||
- base=master
|
- base~=(^main|^master|^stable/)
|
||||||
- label=push
|
- label=push
|
||||||
- author=@tianocore/edk-ii-maintainers
|
|
||||||
- status-success=tianocore.PatchCheck
|
|
||||||
- status-success=Ubuntu GCC5 PR
|
|
||||||
- status-success=Windows VS2019 PR
|
|
||||||
actions:
|
actions:
|
||||||
merge:
|
queue:
|
||||||
strict: true
|
|
||||||
method: rebase
|
method: rebase
|
||||||
|
rebase_fallback: none
|
||||||
- name: Automatically close a PR when all required checks pass and 'push' label is not present
|
name: default
|
||||||
conditions:
|
|
||||||
- base=master
|
|
||||||
- -label=push
|
|
||||||
- -closed
|
|
||||||
- status-success=tianocore.PatchCheck
|
|
||||||
- status-success=Ubuntu GCC5 PR
|
|
||||||
- status-success=Windows VS2019 PR
|
|
||||||
- status-success=Ubuntu GCC5 PR (FINISHED)
|
|
||||||
- status-success=Windows VS2019 PR (FINISHED)
|
|
||||||
actions:
|
|
||||||
close:
|
|
||||||
message: All checks passed. Auto close personal build.
|
|
||||||
|
|
||||||
- name: Post a comment on a PR that can not be merged due to a merge conflict
|
- name: Post a comment on a PR that can not be merged due to a merge conflict
|
||||||
conditions:
|
conditions:
|
||||||
- base=master
|
- base~=(^main|^master|^stable/)
|
||||||
- conflict
|
- conflict
|
||||||
actions:
|
actions:
|
||||||
comment:
|
comment:
|
||||||
message: PR can not be merged due to conflict. Please rebase and resubmit
|
message: PR can not be merged due to conflict. Please rebase and resubmit
|
||||||
|
|
||||||
- name: Automatically close a PR that fails the EDK II Maintainers membership check and 'push' label is present
|
|
||||||
conditions:
|
|
||||||
- base=master
|
|
||||||
- label=push
|
|
||||||
- -author=@tianocore/edk-ii-maintainers
|
|
||||||
actions:
|
|
||||||
close:
|
|
||||||
message: PR submitter is not a member of the Tianocore EDK II Maintainers team
|
|
||||||
|
|
||||||
- name: Post a comment on a PR if PatchCheck fails
|
|
||||||
conditions:
|
|
||||||
- base=master
|
|
||||||
- status-failure=tianocore.PatchCheck
|
|
||||||
actions:
|
|
||||||
comment:
|
|
||||||
message: PR can not be merged due to a PatchCheck failure. Please resolve and resubmit
|
|
||||||
|
|
||||||
- name: Post a comment on a PR if Ubuntu GCC5 fails
|
|
||||||
conditions:
|
|
||||||
- base=master
|
|
||||||
- status-failure=Ubuntu GCC5 PR
|
|
||||||
- status-success=Ubuntu GCC5 PR (FAILED)
|
|
||||||
actions:
|
|
||||||
comment:
|
|
||||||
message: PR can not be merged due to an Ubuntu GCC5 failure. Please resolve and resubmit
|
|
||||||
|
|
||||||
- name: Post a comment on a PR if Windows VS2019 fails
|
|
||||||
conditions:
|
|
||||||
- base=master
|
|
||||||
- status-failure=Windows VS2019 PR
|
|
||||||
- status-success=Windows VS2019 PR (FAILED)
|
|
||||||
actions:
|
|
||||||
comment:
|
|
||||||
message: PR can not be merged due to a Windows VS2019 failure. Please resolve and resubmit
|
|
||||||
|
@@ -2,6 +2,7 @@
|
|||||||
#
|
#
|
||||||
# Copyright (c) Microsoft Corporation.
|
# Copyright (c) Microsoft Corporation.
|
||||||
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
||||||
|
# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.<BR>
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
##
|
##
|
||||||
import os
|
import os
|
||||||
@@ -21,16 +22,24 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
|
|||||||
self.ActualTargets = []
|
self.ActualTargets = []
|
||||||
self.ActualArchitectures = []
|
self.ActualArchitectures = []
|
||||||
self.ActualToolChainTag = ""
|
self.ActualToolChainTag = ""
|
||||||
|
self.UseBuiltInBaseTools = None
|
||||||
|
self.ActualScopes = None
|
||||||
|
|
||||||
# ####################################################################################### #
|
# ####################################################################################### #
|
||||||
# Extra CmdLine configuration #
|
# Extra CmdLine configuration #
|
||||||
# ####################################################################################### #
|
# ####################################################################################### #
|
||||||
|
|
||||||
def AddCommandLineOptions(self, parserObj):
|
def AddCommandLineOptions(self, parserObj):
|
||||||
pass
|
group = parserObj.add_mutually_exclusive_group()
|
||||||
|
group.add_argument("-force_piptools", "--fpt", dest="force_piptools", action="store_true", default=False, help="Force the system to use pip tools")
|
||||||
|
group.add_argument("-no_piptools", "--npt", dest="no_piptools", action="store_true", default=False, help="Force the system to not use pip tools")
|
||||||
|
|
||||||
def RetrieveCommandLineOptions(self, args):
|
def RetrieveCommandLineOptions(self, args):
|
||||||
pass
|
super().RetrieveCommandLineOptions(args)
|
||||||
|
if args.force_piptools:
|
||||||
|
self.UseBuiltInBaseTools = True
|
||||||
|
if args.no_piptools:
|
||||||
|
self.UseBuiltInBaseTools = False
|
||||||
|
|
||||||
# ####################################################################################### #
|
# ####################################################################################### #
|
||||||
# Default Support for this Ci Build #
|
# Default Support for this Ci Build #
|
||||||
@@ -40,7 +49,10 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
|
|||||||
''' return iterable of edk2 packages supported by this build.
|
''' return iterable of edk2 packages supported by this build.
|
||||||
These should be edk2 workspace relative paths '''
|
These should be edk2 workspace relative paths '''
|
||||||
|
|
||||||
return ("ArmVirtPkg",
|
return ("ArmPkg",
|
||||||
|
"ArmPlatformPkg",
|
||||||
|
"ArmVirtPkg",
|
||||||
|
"DynamicTablesPkg",
|
||||||
"EmulatorPkg",
|
"EmulatorPkg",
|
||||||
"MdePkg",
|
"MdePkg",
|
||||||
"MdeModulePkg",
|
"MdeModulePkg",
|
||||||
@@ -50,10 +62,12 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
|
|||||||
"UefiCpuPkg",
|
"UefiCpuPkg",
|
||||||
"FmpDevicePkg",
|
"FmpDevicePkg",
|
||||||
"ShellPkg",
|
"ShellPkg",
|
||||||
|
"StandaloneMmPkg",
|
||||||
"FatPkg",
|
"FatPkg",
|
||||||
"CryptoPkg",
|
"CryptoPkg",
|
||||||
"UnitTestFrameworkPkg",
|
"UnitTestFrameworkPkg",
|
||||||
"OvmfPkg"
|
"OvmfPkg",
|
||||||
|
"RedfishPkg"
|
||||||
)
|
)
|
||||||
|
|
||||||
def GetArchitecturesSupported(self):
|
def GetArchitecturesSupported(self):
|
||||||
@@ -124,19 +138,38 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
|
|||||||
|
|
||||||
def GetActiveScopes(self):
|
def GetActiveScopes(self):
|
||||||
''' return tuple containing scopes that should be active for this process '''
|
''' return tuple containing scopes that should be active for this process '''
|
||||||
|
if self.ActualScopes is None:
|
||||||
scopes = ("cibuild", "edk2-build", "host-based-test")
|
scopes = ("cibuild", "edk2-build", "host-based-test")
|
||||||
|
|
||||||
self.ActualToolChainTag = shell_environment.GetBuildVars().GetValue("TOOL_CHAIN_TAG", "")
|
self.ActualToolChainTag = shell_environment.GetBuildVars().GetValue("TOOL_CHAIN_TAG", "")
|
||||||
|
|
||||||
if GetHostInfo().os.upper() == "LINUX" and self.ActualToolChainTag.upper().startswith("GCC"):
|
is_linux = GetHostInfo().os.upper() == "LINUX"
|
||||||
|
|
||||||
|
if self.UseBuiltInBaseTools is None:
|
||||||
|
is_linux = GetHostInfo().os.upper() == "LINUX"
|
||||||
|
# try and import the pip module for basetools
|
||||||
|
try:
|
||||||
|
import edk2basetools
|
||||||
|
self.UseBuiltInBaseTools = True
|
||||||
|
except ImportError:
|
||||||
|
self.UseBuiltInBaseTools = False
|
||||||
|
pass
|
||||||
|
|
||||||
|
if self.UseBuiltInBaseTools == True:
|
||||||
|
scopes += ('pipbuild-unix',) if is_linux else ('pipbuild-win',)
|
||||||
|
logging.warning("Using Pip Tools based BaseTools")
|
||||||
|
else:
|
||||||
|
logging.warning("Falling back to using in-tree BaseTools")
|
||||||
|
|
||||||
|
if is_linux and self.ActualToolChainTag.upper().startswith("GCC"):
|
||||||
if "AARCH64" in self.ActualArchitectures:
|
if "AARCH64" in self.ActualArchitectures:
|
||||||
scopes += ("gcc_aarch64_linux",)
|
scopes += ("gcc_aarch64_linux",)
|
||||||
if "ARM" in self.ActualArchitectures:
|
if "ARM" in self.ActualArchitectures:
|
||||||
scopes += ("gcc_arm_linux",)
|
scopes += ("gcc_arm_linux",)
|
||||||
if "RISCV64" in self.ActualArchitectures:
|
if "RISCV64" in self.ActualArchitectures:
|
||||||
scopes += ("gcc_riscv64_unknown",)
|
scopes += ("gcc_riscv64_unknown",)
|
||||||
|
self.ActualScopes = scopes
|
||||||
return scopes
|
return self.ActualScopes
|
||||||
|
|
||||||
def GetRequiredSubmodules(self):
|
def GetRequiredSubmodules(self):
|
||||||
''' return iterable containing RequiredSubmodule objects.
|
''' return iterable containing RequiredSubmodule objects.
|
||||||
@@ -155,6 +188,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
|
|||||||
"MdeModulePkg/Library/BrotliCustomDecompressLib/brotli", False))
|
"MdeModulePkg/Library/BrotliCustomDecompressLib/brotli", False))
|
||||||
rs.append(RequiredSubmodule(
|
rs.append(RequiredSubmodule(
|
||||||
"BaseTools/Source/C/BrotliCompress/brotli", False))
|
"BaseTools/Source/C/BrotliCompress/brotli", False))
|
||||||
|
rs.append(RequiredSubmodule(
|
||||||
|
"RedfishPkg/Library/JsonLib/jansson", False))
|
||||||
return rs
|
return rs
|
||||||
|
|
||||||
def GetName(self):
|
def GetName(self):
|
||||||
|
311
.pytool/Plugin/EccCheck/EccCheck.py
Normal file
311
.pytool/Plugin/EccCheck/EccCheck.py
Normal file
@@ -0,0 +1,311 @@
|
|||||||
|
# @file EccCheck.py
|
||||||
|
#
|
||||||
|
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
##
|
||||||
|
|
||||||
|
import os
|
||||||
|
import shutil
|
||||||
|
import re
|
||||||
|
import csv
|
||||||
|
import xml.dom.minidom
|
||||||
|
from typing import List, Dict, Tuple
|
||||||
|
import logging
|
||||||
|
from io import StringIO
|
||||||
|
from edk2toolext.environment import shell_environment
|
||||||
|
from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
|
||||||
|
from edk2toolext.environment.var_dict import VarDict
|
||||||
|
from edk2toollib.utility_functions import RunCmd
|
||||||
|
|
||||||
|
|
||||||
|
class EccCheck(ICiBuildPlugin):
|
||||||
|
"""
|
||||||
|
A CiBuildPlugin that finds the Ecc issues of newly added code in pull request.
|
||||||
|
|
||||||
|
Configuration options:
|
||||||
|
"EccCheck": {
|
||||||
|
"ExceptionList": [],
|
||||||
|
"IgnoreFiles": []
|
||||||
|
},
|
||||||
|
"""
|
||||||
|
|
||||||
|
ReModifyFile = re.compile(r'[B-Q,S-Z]+[\d]*\t(.*)')
|
||||||
|
FindModifyFile = re.compile(r'\+\+\+ b\/(.*)')
|
||||||
|
LineScopePattern = (r'@@ -\d*\,*\d* \+\d*\,*\d* @@.*')
|
||||||
|
LineNumRange = re.compile(r'@@ -\d*\,*\d* \+(\d*)\,*(\d*) @@.*')
|
||||||
|
|
||||||
|
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
|
||||||
|
""" Provide the testcase name and classname for use in reporting
|
||||||
|
testclassname: a descriptive string for the testcase can include whitespace
|
||||||
|
classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
|
||||||
|
|
||||||
|
Args:
|
||||||
|
packagename: string containing name of package to build
|
||||||
|
environment: The VarDict for the test to run in
|
||||||
|
Returns:
|
||||||
|
a tuple containing the testcase name and the classname
|
||||||
|
(testcasename, classname)
|
||||||
|
"""
|
||||||
|
return ("Check for efi coding style for " + packagename, packagename + ".EccCheck")
|
||||||
|
|
||||||
|
##
|
||||||
|
# External function of plugin. This function is used to perform the task of the ci_build_plugin Plugin
|
||||||
|
#
|
||||||
|
# - package is the edk2 path to package. This means workspace/packagepath relative.
|
||||||
|
# - edk2path object configured with workspace and packages path
|
||||||
|
# - PkgConfig Object (dict) for the pkg
|
||||||
|
# - EnvConfig Object
|
||||||
|
# - Plugin Manager Instance
|
||||||
|
# - Plugin Helper Obj Instance
|
||||||
|
# - Junit Logger
|
||||||
|
# - output_stream the StringIO output stream from this plugin via logging
|
||||||
|
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
|
||||||
|
workspace_path = Edk2pathObj.WorkspacePath
|
||||||
|
basetools_path = environment.GetValue("EDK_TOOLS_PATH")
|
||||||
|
python_path = os.path.join(basetools_path, "Source", "Python")
|
||||||
|
env = shell_environment.GetEnvironment()
|
||||||
|
env.set_shell_var('PYTHONPATH', python_path)
|
||||||
|
env.set_shell_var('WORKSPACE', workspace_path)
|
||||||
|
env.set_shell_var('PACKAGES_PATH', os.pathsep.join(Edk2pathObj.PackagePathList))
|
||||||
|
self.ECC_PASS = True
|
||||||
|
self.ApplyConfig(pkgconfig, workspace_path, basetools_path, packagename)
|
||||||
|
modify_dir_list = self.GetModifyDir(packagename)
|
||||||
|
patch = self.GetDiff(packagename)
|
||||||
|
ecc_diff_range = self.GetDiffRange(patch, packagename, workspace_path)
|
||||||
|
self.GenerateEccReport(modify_dir_list, ecc_diff_range, workspace_path, basetools_path)
|
||||||
|
ecc_log = os.path.join(workspace_path, "Ecc.log")
|
||||||
|
self.RevertCode()
|
||||||
|
if self.ECC_PASS:
|
||||||
|
tc.SetSuccess()
|
||||||
|
self.RemoveFile(ecc_log)
|
||||||
|
return 0
|
||||||
|
else:
|
||||||
|
with open(ecc_log, encoding='utf8') as output:
|
||||||
|
ecc_output = output.readlines()
|
||||||
|
for line in ecc_output:
|
||||||
|
logging.error(line.strip())
|
||||||
|
self.RemoveFile(ecc_log)
|
||||||
|
tc.SetFailed("EccCheck failed for {0}".format(packagename), "Ecc detected issues")
|
||||||
|
return 1
|
||||||
|
|
||||||
|
def RevertCode(self) -> None:
|
||||||
|
submoudle_params = "submodule update --init"
|
||||||
|
RunCmd("git", submoudle_params)
|
||||||
|
reset_params = "reset HEAD --hard"
|
||||||
|
RunCmd("git", reset_params)
|
||||||
|
|
||||||
|
def GetDiff(self, pkg: str) -> List[str]:
|
||||||
|
return_buffer = StringIO()
|
||||||
|
params = "diff --unified=0 origin/master HEAD"
|
||||||
|
RunCmd("git", params, outstream=return_buffer)
|
||||||
|
p = return_buffer.getvalue().strip()
|
||||||
|
patch = p.split("\n")
|
||||||
|
return_buffer.close()
|
||||||
|
|
||||||
|
return patch
|
||||||
|
|
||||||
|
def RemoveFile(self, file: str) -> None:
|
||||||
|
if os.path.exists(file):
|
||||||
|
os.remove(file)
|
||||||
|
return
|
||||||
|
|
||||||
|
def GetModifyDir(self, pkg: str) -> List[str]:
|
||||||
|
return_buffer = StringIO()
|
||||||
|
params = "diff --name-status" + ' HEAD' + ' origin/master'
|
||||||
|
RunCmd("git", params, outstream=return_buffer)
|
||||||
|
p1 = return_buffer.getvalue().strip()
|
||||||
|
dir_list = p1.split("\n")
|
||||||
|
return_buffer.close()
|
||||||
|
modify_dir_list = []
|
||||||
|
for modify_dir in dir_list:
|
||||||
|
file_path = self.ReModifyFile.findall(modify_dir)
|
||||||
|
if file_path:
|
||||||
|
file_dir = os.path.dirname(file_path[0])
|
||||||
|
else:
|
||||||
|
continue
|
||||||
|
if pkg in file_dir and file_dir != pkg:
|
||||||
|
modify_dir_list.append('%s' % file_dir)
|
||||||
|
else:
|
||||||
|
continue
|
||||||
|
|
||||||
|
modify_dir_list = list(set(modify_dir_list))
|
||||||
|
return modify_dir_list
|
||||||
|
|
||||||
|
def GetDiffRange(self, patch_diff: List[str], pkg: str, workingdir: str) -> Dict[str, List[Tuple[int, int]]]:
|
||||||
|
IsDelete = True
|
||||||
|
StartCheck = False
|
||||||
|
range_directory: Dict[str, List[Tuple[int, int]]] = {}
|
||||||
|
for line in patch_diff:
|
||||||
|
modify_file = self.FindModifyFile.findall(line)
|
||||||
|
if modify_file and pkg in modify_file[0] and not StartCheck and os.path.isfile(modify_file[0]):
|
||||||
|
modify_file_comment_dic = self.GetCommentRange(modify_file[0], workingdir)
|
||||||
|
IsDelete = False
|
||||||
|
StartCheck = True
|
||||||
|
modify_file_dic = modify_file[0]
|
||||||
|
modify_file_dic = modify_file_dic.replace("/", os.sep)
|
||||||
|
range_directory[modify_file_dic] = []
|
||||||
|
elif line.startswith('--- '):
|
||||||
|
StartCheck = False
|
||||||
|
elif re.match(self.LineScopePattern, line, re.I) and not IsDelete and StartCheck:
|
||||||
|
start_line = self.LineNumRange.search(line).group(1)
|
||||||
|
line_range = self.LineNumRange.search(line).group(2)
|
||||||
|
if not line_range:
|
||||||
|
line_range = '1'
|
||||||
|
range_directory[modify_file_dic].append((int(start_line), int(start_line) + int(line_range) - 1))
|
||||||
|
for i in modify_file_comment_dic:
|
||||||
|
if int(i[0]) <= int(start_line) <= int(i[1]):
|
||||||
|
range_directory[modify_file_dic].append(i)
|
||||||
|
return range_directory
|
||||||
|
|
||||||
|
def GetCommentRange(self, modify_file: str, workingdir: str) -> List[Tuple[int, int]]:
|
||||||
|
modify_file_path = os.path.join(workingdir, modify_file)
|
||||||
|
with open(modify_file_path) as f:
|
||||||
|
line_no = 1
|
||||||
|
comment_range: List[Tuple[int, int]] = []
|
||||||
|
Start = False
|
||||||
|
for line in f:
|
||||||
|
if line.startswith('/**'):
|
||||||
|
start_no = line_no
|
||||||
|
Start = True
|
||||||
|
if line.startswith('**/') and Start:
|
||||||
|
end_no = line_no
|
||||||
|
Start = False
|
||||||
|
comment_range.append((int(start_no), int(end_no)))
|
||||||
|
line_no += 1
|
||||||
|
|
||||||
|
if comment_range and comment_range[0][0] == 1:
|
||||||
|
del comment_range[0]
|
||||||
|
return comment_range
|
||||||
|
|
||||||
|
def GenerateEccReport(self, modify_dir_list: List[str], ecc_diff_range: Dict[str, List[Tuple[int, int]]],
|
||||||
|
workspace_path: str, basetools_path: str) -> None:
|
||||||
|
ecc_need = False
|
||||||
|
ecc_run = True
|
||||||
|
config = os.path.join(basetools_path, "Source", "Python", "Ecc", "config.ini")
|
||||||
|
exception = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
|
||||||
|
report = os.path.join(workspace_path, "Ecc.csv")
|
||||||
|
for modify_dir in modify_dir_list:
|
||||||
|
target = os.path.join(workspace_path, modify_dir)
|
||||||
|
logging.info('Run ECC tool for the commit in %s' % modify_dir)
|
||||||
|
ecc_need = True
|
||||||
|
ecc_params = "-c {0} -e {1} -t {2} -r {3}".format(config, exception, target, report)
|
||||||
|
return_code = RunCmd("Ecc", ecc_params, workingdir=workspace_path)
|
||||||
|
if return_code != 0:
|
||||||
|
ecc_run = False
|
||||||
|
break
|
||||||
|
if not ecc_run:
|
||||||
|
logging.error('Fail to run ECC tool')
|
||||||
|
self.ParseEccReport(ecc_diff_range, workspace_path)
|
||||||
|
|
||||||
|
if not ecc_need:
|
||||||
|
logging.info("Doesn't need run ECC check")
|
||||||
|
|
||||||
|
revert_params = "checkout -- {}".format(exception)
|
||||||
|
RunCmd("git", revert_params)
|
||||||
|
return
|
||||||
|
|
||||||
|
def ParseEccReport(self, ecc_diff_range: Dict[str, List[Tuple[int, int]]], workspace_path: str) -> None:
|
||||||
|
ecc_log = os.path.join(workspace_path, "Ecc.log")
|
||||||
|
ecc_csv = os.path.join(workspace_path, "Ecc.csv")
|
||||||
|
row_lines = []
|
||||||
|
ignore_error_code = self.GetIgnoreErrorCode()
|
||||||
|
if os.path.exists(ecc_csv):
|
||||||
|
with open(ecc_csv) as csv_file:
|
||||||
|
reader = csv.reader(csv_file)
|
||||||
|
for row in reader:
|
||||||
|
for modify_file in ecc_diff_range:
|
||||||
|
if modify_file in row[3]:
|
||||||
|
for i in ecc_diff_range[modify_file]:
|
||||||
|
line_no = int(row[4])
|
||||||
|
if i[0] <= line_no <= i[1] and row[1] not in ignore_error_code:
|
||||||
|
row[0] = '\nEFI coding style error'
|
||||||
|
row[1] = 'Error code: ' + row[1]
|
||||||
|
row[3] = 'file: ' + row[3]
|
||||||
|
row[4] = 'Line number: ' + row[4]
|
||||||
|
row_line = '\n *'.join(row)
|
||||||
|
row_lines.append(row_line)
|
||||||
|
break
|
||||||
|
break
|
||||||
|
if row_lines:
|
||||||
|
self.ECC_PASS = False
|
||||||
|
|
||||||
|
with open(ecc_log, 'a') as log:
|
||||||
|
all_line = '\n'.join(row_lines)
|
||||||
|
all_line = all_line + '\n'
|
||||||
|
log.writelines(all_line)
|
||||||
|
return
|
||||||
|
|
||||||
|
def ApplyConfig(self, pkgconfig: Dict[str, List[str]], workspace_path: str, basetools_path: str, pkg: str) -> None:
|
||||||
|
if "IgnoreFiles" in pkgconfig:
|
||||||
|
for a in pkgconfig["IgnoreFiles"]:
|
||||||
|
a = os.path.join(workspace_path, pkg, a)
|
||||||
|
a = a.replace(os.sep, "/")
|
||||||
|
|
||||||
|
logging.info("Ignoring Files {0}".format(a))
|
||||||
|
if os.path.exists(a):
|
||||||
|
if os.path.isfile(a):
|
||||||
|
self.RemoveFile(a)
|
||||||
|
elif os.path.isdir(a):
|
||||||
|
shutil.rmtree(a)
|
||||||
|
else:
|
||||||
|
logging.error("EccCheck.IgnoreInf -> {0} not found in filesystem. Invalid ignore files".format(a))
|
||||||
|
|
||||||
|
if "ExceptionList" in pkgconfig:
|
||||||
|
exception_list = pkgconfig["ExceptionList"]
|
||||||
|
exception_xml = os.path.join(basetools_path, "Source", "Python", "Ecc", "exception.xml")
|
||||||
|
try:
|
||||||
|
logging.info("Appending exceptions")
|
||||||
|
self.AppendException(exception_list, exception_xml)
|
||||||
|
except Exception as e:
|
||||||
|
logging.error("Fail to apply exceptions")
|
||||||
|
raise e
|
||||||
|
return
|
||||||
|
|
||||||
|
def AppendException(self, exception_list: List[str], exception_xml: str) -> None:
|
||||||
|
error_code_list = exception_list[::2]
|
||||||
|
keyword_list = exception_list[1::2]
|
||||||
|
dom_tree = xml.dom.minidom.parse(exception_xml)
|
||||||
|
root_node = dom_tree.documentElement
|
||||||
|
for error_code, keyword in zip(error_code_list, keyword_list):
|
||||||
|
customer_node = dom_tree.createElement("Exception")
|
||||||
|
keyword_node = dom_tree.createElement("KeyWord")
|
||||||
|
keyword_node_text_value = dom_tree.createTextNode(keyword)
|
||||||
|
keyword_node.appendChild(keyword_node_text_value)
|
||||||
|
customer_node.appendChild(keyword_node)
|
||||||
|
error_code_node = dom_tree.createElement("ErrorID")
|
||||||
|
error_code_text_value = dom_tree.createTextNode(error_code)
|
||||||
|
error_code_node.appendChild(error_code_text_value)
|
||||||
|
customer_node.appendChild(error_code_node)
|
||||||
|
root_node.appendChild(customer_node)
|
||||||
|
with open(exception_xml, 'w') as f:
|
||||||
|
dom_tree.writexml(f, indent='', addindent='', newl='\n', encoding='UTF-8')
|
||||||
|
return
|
||||||
|
|
||||||
|
def GetIgnoreErrorCode(self) -> set:
|
||||||
|
"""
|
||||||
|
Below are kinds of error code that are accurate in ecc scanning of edk2 level.
|
||||||
|
But EccCheck plugin is partial scanning so they are always false positive issues.
|
||||||
|
The mapping relationship of error code and error message is listed BaseTools/Sourc/Python/Ecc/EccToolError.py
|
||||||
|
"""
|
||||||
|
ignore_error_code = {
|
||||||
|
"10000",
|
||||||
|
"10001",
|
||||||
|
"10002",
|
||||||
|
"10003",
|
||||||
|
"10004",
|
||||||
|
"10005",
|
||||||
|
"10006",
|
||||||
|
"10007",
|
||||||
|
"10008",
|
||||||
|
"10009",
|
||||||
|
"10010",
|
||||||
|
"10011",
|
||||||
|
"10012",
|
||||||
|
"10013",
|
||||||
|
"10015",
|
||||||
|
"10016",
|
||||||
|
"10017",
|
||||||
|
"10022",
|
||||||
|
}
|
||||||
|
return ignore_error_code
|
11
.pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
Normal file
11
.pytool/Plugin/EccCheck/EccCheck_plug_in.yaml
Normal file
@@ -0,0 +1,11 @@
|
|||||||
|
## @file
|
||||||
|
# CiBuildPlugin used to check Ecc issues
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
##
|
||||||
|
{
|
||||||
|
"scope": "cibuild",
|
||||||
|
"name": "EccCheck Test",
|
||||||
|
"module": "EccCheck"
|
||||||
|
}
|
15
.pytool/Plugin/EccCheck/Readme.md
Normal file
15
.pytool/Plugin/EccCheck/Readme.md
Normal file
@@ -0,0 +1,15 @@
|
|||||||
|
# EFI Coding style Check Plugin
|
||||||
|
|
||||||
|
This CiBuildPlugin finds the Ecc issues of newly added code in pull request.
|
||||||
|
|
||||||
|
## Configuration
|
||||||
|
|
||||||
|
The plugin can be configured to ignore certain files and issues.
|
||||||
|
|
||||||
|
"EccCheck": {
|
||||||
|
"ExceptionList": [],
|
||||||
|
"IgnoreFiles": []
|
||||||
|
},
|
||||||
|
"""
|
||||||
|
|
||||||
|
OPTIONAL List of file to ignore.
|
115
.pytool/Plugin/LicenseCheck/LicenseCheck.py
Normal file
115
.pytool/Plugin/LicenseCheck/LicenseCheck.py
Normal file
@@ -0,0 +1,115 @@
|
|||||||
|
# @file LicenseCheck.py
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
##
|
||||||
|
|
||||||
|
import os
|
||||||
|
import logging
|
||||||
|
import re
|
||||||
|
from io import StringIO
|
||||||
|
from typing import List, Tuple
|
||||||
|
from edk2toolext.environment.plugintypes.ci_build_plugin import ICiBuildPlugin
|
||||||
|
from edk2toolext.environment.var_dict import VarDict
|
||||||
|
from edk2toollib.utility_functions import RunCmd
|
||||||
|
|
||||||
|
|
||||||
|
class LicenseCheck(ICiBuildPlugin):
|
||||||
|
|
||||||
|
"""
|
||||||
|
A CiBuildPlugin to check the license for new added files.
|
||||||
|
|
||||||
|
Configuration options:
|
||||||
|
"LicenseCheck": {
|
||||||
|
"IgnoreFiles": []
|
||||||
|
},
|
||||||
|
"""
|
||||||
|
|
||||||
|
license_format_preflix = 'SPDX-License-Identifier'
|
||||||
|
|
||||||
|
bsd2_patent = 'BSD-2-Clause-Patent'
|
||||||
|
|
||||||
|
Readdedfileformat = re.compile(r'\+\+\+ b\/(.*)')
|
||||||
|
|
||||||
|
file_extension_list = [".c", ".h", ".inf", ".dsc", ".dec", ".py", ".bat", ".sh", ".uni", ".yaml",
|
||||||
|
".fdf", ".inc", "yml", ".asm", ".asm16", ".asl", ".vfr", ".s", ".S", ".aslc",
|
||||||
|
".nasm", ".nasmb", ".idf", ".Vfr", ".H"]
|
||||||
|
|
||||||
|
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
|
||||||
|
""" Provide the testcase name and classname for use in reporting
|
||||||
|
testclassname: a descriptive string for the testcase can include whitespace
|
||||||
|
classname: should be patterned <packagename>.<plugin>.<optionally any unique condition>
|
||||||
|
|
||||||
|
Args:
|
||||||
|
packagename: string containing name of package to build
|
||||||
|
environment: The VarDict for the test to run in
|
||||||
|
Returns:
|
||||||
|
a tuple containing the testcase name and the classname
|
||||||
|
(testcasename, classname)
|
||||||
|
"""
|
||||||
|
return ("Check for license for " + packagename, packagename + ".LicenseCheck")
|
||||||
|
|
||||||
|
##
|
||||||
|
# External function of plugin. This function is used to perform the task of the ci_build_plugin Plugin
|
||||||
|
#
|
||||||
|
# - package is the edk2 path to package. This means workspace/packagepath relative.
|
||||||
|
# - edk2path object configured with workspace and packages path
|
||||||
|
# - PkgConfig Object (dict) for the pkg
|
||||||
|
# - EnvConfig Object
|
||||||
|
# - Plugin Manager Instance
|
||||||
|
# - Plugin Helper Obj Instance
|
||||||
|
# - Junit Logger
|
||||||
|
# - output_stream the StringIO output stream from this plugin via logging
|
||||||
|
def RunBuildPlugin(self, packagename, Edk2pathObj, pkgconfig, environment, PLM, PLMHelper, tc, output_stream=None):
|
||||||
|
return_buffer = StringIO()
|
||||||
|
params = "diff --unified=0 origin/master HEAD"
|
||||||
|
RunCmd("git", params, outstream=return_buffer)
|
||||||
|
p = return_buffer.getvalue().strip()
|
||||||
|
patch = p.split("\n")
|
||||||
|
return_buffer.close()
|
||||||
|
|
||||||
|
ignore_files = []
|
||||||
|
if "IgnoreFiles" in pkgconfig:
|
||||||
|
ignore_files = pkgconfig["IgnoreFiles"]
|
||||||
|
|
||||||
|
self.ok = True
|
||||||
|
self.startcheck = False
|
||||||
|
self.license = True
|
||||||
|
self.all_file_pass = True
|
||||||
|
count = len(patch)
|
||||||
|
line_index = 0
|
||||||
|
for line in patch:
|
||||||
|
if line.startswith('--- /dev/null'):
|
||||||
|
nextline = patch[line_index + 1]
|
||||||
|
added_file = self.Readdedfileformat.search(nextline).group(1)
|
||||||
|
added_file_extension = os.path.splitext(added_file)[1]
|
||||||
|
if added_file_extension in self.file_extension_list and packagename in added_file:
|
||||||
|
if (self.IsIgnoreFile(added_file, ignore_files)):
|
||||||
|
line_index = line_index + 1
|
||||||
|
continue
|
||||||
|
self.startcheck = True
|
||||||
|
self.license = False
|
||||||
|
if self.startcheck and self.license_format_preflix in line:
|
||||||
|
if self.bsd2_patent in line:
|
||||||
|
self.license = True
|
||||||
|
if line_index + 1 == count or patch[line_index + 1].startswith('diff --') and self.startcheck:
|
||||||
|
if not self.license:
|
||||||
|
self.all_file_pass = False
|
||||||
|
error_message = "Invalid license in: " + added_file + " Hint: Only BSD-2-Clause-Patent is accepted."
|
||||||
|
logging.error(error_message)
|
||||||
|
self.startcheck = False
|
||||||
|
self.license = True
|
||||||
|
line_index = line_index + 1
|
||||||
|
|
||||||
|
if self.all_file_pass:
|
||||||
|
tc.SetSuccess()
|
||||||
|
return 0
|
||||||
|
else:
|
||||||
|
tc.SetFailed("License Check {0} Failed. ".format(packagename), "LICENSE_CHECK_FAILED")
|
||||||
|
return 1
|
||||||
|
|
||||||
|
def IsIgnoreFile(self, file: str, ignore_files: List[str]) -> bool:
|
||||||
|
for f in ignore_files:
|
||||||
|
if f in file:
|
||||||
|
return True
|
||||||
|
return False
|
11
.pytool/Plugin/LicenseCheck/LicenseCheck_plug_in.yaml
Normal file
11
.pytool/Plugin/LicenseCheck/LicenseCheck_plug_in.yaml
Normal file
@@ -0,0 +1,11 @@
|
|||||||
|
## @file
|
||||||
|
# CiBuildPlugin used to check license issues for new added files
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020, Intel Corporation. All rights reserved.
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
##
|
||||||
|
{
|
||||||
|
"scope": "cibuild",
|
||||||
|
"name": "License Check Test",
|
||||||
|
"module": "LicenseCheck"
|
||||||
|
}
|
17
.pytool/Plugin/LicenseCheck/Readme.md
Normal file
17
.pytool/Plugin/LicenseCheck/Readme.md
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
# License Check Plugin
|
||||||
|
|
||||||
|
This CiBuildPlugin scans all new added files in a package to make sure code
|
||||||
|
is contributed under BSD-2-Clause-Patent.
|
||||||
|
|
||||||
|
## Configuration
|
||||||
|
|
||||||
|
The plugin can be configured to ignore certain files.
|
||||||
|
|
||||||
|
``` yaml
|
||||||
|
"LicenseCheck": {
|
||||||
|
"IgnoreFiles": []
|
||||||
|
}
|
||||||
|
```
|
||||||
|
### IgnoreFiles
|
||||||
|
|
||||||
|
OPTIONAL List of file to ignore.
|
@@ -37,12 +37,12 @@ class SpellCheck(ICiBuildPlugin):
|
|||||||
#
|
#
|
||||||
# A package can remove any of these using IgnoreStandardPaths
|
# A package can remove any of these using IgnoreStandardPaths
|
||||||
#
|
#
|
||||||
STANDARD_PLUGIN_DEFINED_PATHS = ["*.c", "*.h",
|
STANDARD_PLUGIN_DEFINED_PATHS = ("*.c", "*.h",
|
||||||
"*.nasm", "*.asm", "*.masm", "*.s",
|
"*.nasm", "*.asm", "*.masm", "*.s",
|
||||||
"*.asl",
|
"*.asl",
|
||||||
"*.dsc", "*.dec", "*.fdf", "*.inf",
|
"*.dsc", "*.dec", "*.fdf", "*.inf",
|
||||||
"*.md", "*.txt"
|
"*.md", "*.txt"
|
||||||
]
|
)
|
||||||
|
|
||||||
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
|
def GetTestName(self, packagename: str, environment: VarDict) -> tuple:
|
||||||
""" Provide the testcase name and classname for use in reporting
|
""" Provide the testcase name and classname for use in reporting
|
||||||
@@ -107,7 +107,8 @@ class SpellCheck(ICiBuildPlugin):
|
|||||||
version_aggregator.GetVersionAggregator().ReportVersion(
|
version_aggregator.GetVersionAggregator().ReportVersion(
|
||||||
"CSpell", cspell_version, version_aggregator.VersionTypes.INFO)
|
"CSpell", cspell_version, version_aggregator.VersionTypes.INFO)
|
||||||
|
|
||||||
package_relative_paths_to_spell_check = SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS
|
# copy the default as a list
|
||||||
|
package_relative_paths_to_spell_check = list(SpellCheck.STANDARD_PLUGIN_DEFINED_PATHS)
|
||||||
|
|
||||||
#
|
#
|
||||||
# Allow the ci.yaml to remove any of the above standard paths
|
# Allow the ci.yaml to remove any of the above standard paths
|
||||||
@@ -133,7 +134,8 @@ class SpellCheck(ICiBuildPlugin):
|
|||||||
#
|
#
|
||||||
relpath = os.path.relpath(abs_pkg_path)
|
relpath = os.path.relpath(abs_pkg_path)
|
||||||
cpsell_paths = " ".join(
|
cpsell_paths = " ".join(
|
||||||
[f"{relpath}/**/{x}" for x in package_relative_paths_to_spell_check])
|
# Double quote each path to defer expansion to cspell parameters
|
||||||
|
[f'"{relpath}/**/{x}"' for x in package_relative_paths_to_spell_check])
|
||||||
|
|
||||||
# Make the config file
|
# Make the config file
|
||||||
config_file_path = os.path.join(
|
config_file_path = os.path.join(
|
||||||
|
@@ -178,5 +178,6 @@
|
|||||||
"vcruntimed",
|
"vcruntimed",
|
||||||
"ucrtd",
|
"ucrtd",
|
||||||
"msvcrtd",
|
"msvcrtd",
|
||||||
|
"XIPFLAGS"
|
||||||
]
|
]
|
||||||
}
|
}
|
||||||
|
@@ -4,11 +4,11 @@
|
|||||||
|
|
||||||
| Package | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues |
|
| Package | Windows VS2019 (IA32/X64)| Ubuntu GCC (IA32/X64/ARM/AARCH64) | Known Issues |
|
||||||
| :---- | :----- | :---- | :--- |
|
| :---- | :----- | :---- | :--- |
|
||||||
| ArmPkg |
|
| ArmPkg | | :heavy_check_mark: |
|
||||||
| ArmPlatformPkg |
|
| ArmPlatformPkg | | :heavy_check_mark: |
|
||||||
| ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README |
|
| ArmVirtPkg | SEE PACKAGE README | SEE PACKAGE README |
|
||||||
| CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
|
| CryptoPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode
|
||||||
| DynamicTablesPkg |
|
| DynamicTablesPkg | | :heavy_check_mark: |
|
||||||
| EmbeddedPkg |
|
| EmbeddedPkg |
|
||||||
| EmulatorPkg | SEE PACKAGE README | SEE PACKAGE README | Spell checking in audit mode
|
| EmulatorPkg | SEE PACKAGE README | SEE PACKAGE README | Spell checking in audit mode
|
||||||
| FatPkg | :heavy_check_mark: | :heavy_check_mark: |
|
| FatPkg | :heavy_check_mark: | :heavy_check_mark: |
|
||||||
@@ -24,7 +24,7 @@
|
|||||||
| ShellPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 3 modules are not being built by DSC
|
| ShellPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 3 modules are not being built by DSC
|
||||||
| SignedCapsulePkg |
|
| SignedCapsulePkg |
|
||||||
| SourceLevelDebugPkg |
|
| SourceLevelDebugPkg |
|
||||||
| StandaloneMmPkg |
|
| StandaloneMmPkg | :heavy_check_mark: | :heavy_check_mark: |
|
||||||
| UefiCpuPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 2 binary modules not being built by DSC
|
| UefiCpuPkg | :heavy_check_mark: | :heavy_check_mark: | Spell checking in audit mode, 2 binary modules not being built by DSC
|
||||||
| UefiPayloadPkg |
|
| UefiPayloadPkg |
|
||||||
| UnitTestFrameworkPkg | :heavy_check_mark: | :heavy_check_mark: |
|
| UnitTestFrameworkPkg | :heavy_check_mark: | :heavy_check_mark: |
|
||||||
@@ -254,6 +254,16 @@ Install
|
|||||||
|
|
||||||
More cspell info: https://github.com/streetsidesoftware/cspell
|
More cspell info: https://github.com/streetsidesoftware/cspell
|
||||||
|
|
||||||
|
### License Checking - LicenseCheck
|
||||||
|
|
||||||
|
Scans all new added files in a package to make sure code is contributed under
|
||||||
|
BSD-2-Clause-Patent.
|
||||||
|
|
||||||
|
### Ecc tool - EccCheck
|
||||||
|
|
||||||
|
Run the Ecc tool on the package. The Ecc tool is available in the BaseTools
|
||||||
|
package. It checks that the code complies to the EDKII coding standard.
|
||||||
|
|
||||||
## PyTool Scopes
|
## PyTool Scopes
|
||||||
|
|
||||||
Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning
|
Scopes are how the PyTool ext_dep, path_env, and plugins are activated. Meaning
|
||||||
|
240
ArmPkg/ArmPkg.ci.yaml
Normal file
240
ArmPkg/ArmPkg.ci.yaml
Normal file
@@ -0,0 +1,240 @@
|
|||||||
|
## @file
|
||||||
|
# CI configuration for ArmPkg
|
||||||
|
#
|
||||||
|
# Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
##
|
||||||
|
{
|
||||||
|
## options defined .pytool/Plugin/LicenseCheck
|
||||||
|
"LicenseCheck": {
|
||||||
|
"IgnoreFiles": []
|
||||||
|
},
|
||||||
|
|
||||||
|
"EccCheck": {
|
||||||
|
## Exception sample looks like below:
|
||||||
|
## "ExceptionList": [
|
||||||
|
## "<ErrorID>", "<KeyWord>"
|
||||||
|
## ]
|
||||||
|
"ExceptionList": [
|
||||||
|
],
|
||||||
|
## Both file path and directory path are accepted.
|
||||||
|
"IgnoreFiles": [
|
||||||
|
"Library/ArmSoftFloatLib/berkeley-softfloat-3"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/CompilerPlugin
|
||||||
|
"CompilerPlugin": {
|
||||||
|
"DscPath": "ArmPkg.dsc"
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/HostUnitTestCompilerPlugin
|
||||||
|
"HostUnitTestCompilerPlugin": {
|
||||||
|
"DscPath": "" # Don't support this test
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/CharEncodingCheck
|
||||||
|
"CharEncodingCheck": {
|
||||||
|
"IgnoreFiles": []
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/DependencyCheck
|
||||||
|
"DependencyCheck": {
|
||||||
|
"AcceptableDependencies": [
|
||||||
|
"ArmPlatformPkg/ArmPlatformPkg.dec",
|
||||||
|
"ArmPkg/ArmPkg.dec",
|
||||||
|
"EmbeddedPkg/EmbeddedPkg.dec",
|
||||||
|
"MdeModulePkg/MdeModulePkg.dec",
|
||||||
|
"MdePkg/MdePkg.dec",
|
||||||
|
"ShellPkg/ShellPkg.dec"
|
||||||
|
],
|
||||||
|
# For host based unit tests
|
||||||
|
"AcceptableDependencies-HOST_APPLICATION":[
|
||||||
|
"UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec"
|
||||||
|
],
|
||||||
|
# For UEFI shell based apps
|
||||||
|
"AcceptableDependencies-UEFI_APPLICATION":[],
|
||||||
|
"IgnoreInf": []
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/DscCompleteCheck
|
||||||
|
"DscCompleteCheck": {
|
||||||
|
"IgnoreInf": [],
|
||||||
|
"DscPath": "ArmPkg.dsc"
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/HostUnitTestDscCompleteCheck
|
||||||
|
"HostUnitTestDscCompleteCheck": {
|
||||||
|
"IgnoreInf": [""],
|
||||||
|
"DscPath": "" # Don't support this test
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/GuidCheck
|
||||||
|
"GuidCheck": {
|
||||||
|
"IgnoreGuidName": [],
|
||||||
|
"IgnoreGuidValue": [],
|
||||||
|
"IgnoreFoldersAndFiles": [],
|
||||||
|
"IgnoreDuplicates": [],
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/LibraryClassCheck
|
||||||
|
"LibraryClassCheck": {
|
||||||
|
"IgnoreHeaderFile": []
|
||||||
|
},
|
||||||
|
|
||||||
|
## options defined .pytool/Plugin/SpellCheck
|
||||||
|
"SpellCheck": {
|
||||||
|
"AuditOnly": False,
|
||||||
|
"IgnoreFiles": [
|
||||||
|
"Library/ArmSoftFloatLib/berkeley-softfloat-3/**"
|
||||||
|
], # use gitignore syntax to ignore errors
|
||||||
|
# in matching files
|
||||||
|
"ExtendWords": [
|
||||||
|
"api's",
|
||||||
|
"ackintid",
|
||||||
|
"actlr",
|
||||||
|
"aeabi",
|
||||||
|
"asedis",
|
||||||
|
"ashldi",
|
||||||
|
"ashrdi",
|
||||||
|
"baddr",
|
||||||
|
"ccidx",
|
||||||
|
"ccsidr",
|
||||||
|
"clidr",
|
||||||
|
"clrex",
|
||||||
|
"clzsi",
|
||||||
|
"cnthctl",
|
||||||
|
"cortexa",
|
||||||
|
"cpacr",
|
||||||
|
"cpuactlr",
|
||||||
|
"csselr",
|
||||||
|
"ctzsi",
|
||||||
|
"cygdrive",
|
||||||
|
"cygpaths",
|
||||||
|
"datas",
|
||||||
|
"dcmpeq",
|
||||||
|
"dcmpge",
|
||||||
|
"dcmpgt",
|
||||||
|
"dcmple",
|
||||||
|
"dcmplt",
|
||||||
|
"ddisable",
|
||||||
|
"divdi",
|
||||||
|
"divsi",
|
||||||
|
"dmdepkg",
|
||||||
|
"dpref",
|
||||||
|
"drsub",
|
||||||
|
"fcmpeq",
|
||||||
|
"fcmpge",
|
||||||
|
"fcmpgt",
|
||||||
|
"fcmple",
|
||||||
|
"fcmplt",
|
||||||
|
"ffreestanding",
|
||||||
|
"frsub",
|
||||||
|
"hisilicon",
|
||||||
|
"iccabpr",
|
||||||
|
"iccbpr",
|
||||||
|
"icciar",
|
||||||
|
"iccicr",
|
||||||
|
"icciidr",
|
||||||
|
"iccpir",
|
||||||
|
"iccpmr",
|
||||||
|
"iccrpr",
|
||||||
|
"icdabr",
|
||||||
|
"icdicer",
|
||||||
|
"icdicfr",
|
||||||
|
"icdicpr",
|
||||||
|
"icdictr",
|
||||||
|
"icdiidr",
|
||||||
|
"icdiser",
|
||||||
|
"icdisr",
|
||||||
|
"icdppisr",
|
||||||
|
"icdsgir",
|
||||||
|
"icdspr",
|
||||||
|
"icenabler",
|
||||||
|
"intid",
|
||||||
|
"ipriority",
|
||||||
|
"irouter",
|
||||||
|
"isenabler",
|
||||||
|
"istatus",
|
||||||
|
"itargets",
|
||||||
|
"lable",
|
||||||
|
"ldivmod",
|
||||||
|
"ldmdb",
|
||||||
|
"ldmia",
|
||||||
|
"ldrbt",
|
||||||
|
"ldrex",
|
||||||
|
"ldrexb",
|
||||||
|
"ldrexd",
|
||||||
|
"ldrexh",
|
||||||
|
"ldrhbt",
|
||||||
|
"ldrht",
|
||||||
|
"ldrsb",
|
||||||
|
"ldrsbt",
|
||||||
|
"ldrsh",
|
||||||
|
"lshrdi",
|
||||||
|
"moddi",
|
||||||
|
"modsi",
|
||||||
|
"mpcore",
|
||||||
|
"mpidr",
|
||||||
|
"muldi",
|
||||||
|
"mullu",
|
||||||
|
"nonshareable",
|
||||||
|
"nsacr",
|
||||||
|
"nsasedis",
|
||||||
|
"nuvia",
|
||||||
|
"oldit",
|
||||||
|
"pcten",
|
||||||
|
"plpis",
|
||||||
|
"procno",
|
||||||
|
"readc",
|
||||||
|
"revsh",
|
||||||
|
"rfedb",
|
||||||
|
"sctlr",
|
||||||
|
"smccc",
|
||||||
|
"smlabb",
|
||||||
|
"smlabt",
|
||||||
|
"smlad",
|
||||||
|
"smladx",
|
||||||
|
"smlatb",
|
||||||
|
"smlatt",
|
||||||
|
"smlawb",
|
||||||
|
"smlawt",
|
||||||
|
"smlsd",
|
||||||
|
"smlsdx",
|
||||||
|
"smmla",
|
||||||
|
"smmlar",
|
||||||
|
"smmls",
|
||||||
|
"smmlsr",
|
||||||
|
"sourcery",
|
||||||
|
"srsdb",
|
||||||
|
"ssacr",
|
||||||
|
"stmdb",
|
||||||
|
"stmia",
|
||||||
|
"strbt",
|
||||||
|
"strexb",
|
||||||
|
"strexd",
|
||||||
|
"strexh",
|
||||||
|
"strht",
|
||||||
|
"switchu",
|
||||||
|
"tpidrurw",
|
||||||
|
"ttbcr",
|
||||||
|
"typer",
|
||||||
|
"ucmpdi",
|
||||||
|
"udivdi",
|
||||||
|
"udivmoddi",
|
||||||
|
"udivsi",
|
||||||
|
"uefi's",
|
||||||
|
"uldiv",
|
||||||
|
"umoddi",
|
||||||
|
"umodsi",
|
||||||
|
"usada",
|
||||||
|
"vlpis",
|
||||||
|
"writec"
|
||||||
|
], # words to extend to the dictionary for this package
|
||||||
|
"IgnoreStandardPaths": [ # Standard Plugin defined paths that
|
||||||
|
"*.asm", "*.s" # should be ignore
|
||||||
|
],
|
||||||
|
"AdditionalIncludePaths": [] # Additional paths to spell check
|
||||||
|
# (wildcards supported)
|
||||||
|
}
|
||||||
|
}
|
@@ -2,7 +2,7 @@
|
|||||||
# ARM processor package.
|
# ARM processor package.
|
||||||
#
|
#
|
||||||
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
|
# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
@@ -27,15 +27,68 @@
|
|||||||
Include # Root include for the package
|
Include # Root include for the package
|
||||||
|
|
||||||
[LibraryClasses.common]
|
[LibraryClasses.common]
|
||||||
ArmLib|Include/Library/ArmLib.h
|
## @libraryclass Convert Arm instructions to a human readable format.
|
||||||
ArmMmuLib|Include/Library/ArmMmuLib.h
|
#
|
||||||
SemihostLib|Include/Library/Semihosting.h
|
|
||||||
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
|
|
||||||
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
|
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an interface to Arm generic counters.
|
||||||
|
#
|
||||||
|
ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an interface to initialize a
|
||||||
|
# Generic Interrupt Controller (GIC).
|
||||||
|
#
|
||||||
ArmGicArchLib|Include/Library/ArmGicArchLib.h
|
ArmGicArchLib|Include/Library/ArmGicArchLib.h
|
||||||
ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h
|
|
||||||
|
## @libraryclass Provides a Generic Interrupt Controller (GIC)
|
||||||
|
# configuration interface.
|
||||||
|
#
|
||||||
|
ArmGicLib|Include/Library/ArmGicLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a HyperVisor Call (HVC) interface.
|
||||||
|
#
|
||||||
|
ArmHvcLib|Include/Library/ArmHvcLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an interface to Arm registers.
|
||||||
|
#
|
||||||
|
ArmLib|Include/Library/ArmLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a Mmu interface.
|
||||||
|
#
|
||||||
|
ArmMmuLib|Include/Library/ArmMmuLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
|
||||||
|
# for the System Control and Management Interface (SCMI).
|
||||||
|
#
|
||||||
|
ArmMtlLib|Include/Library/ArmMtlLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a System Monitor Call (SMC) interface.
|
||||||
|
#
|
||||||
|
ArmSmcLib|Include/Library/ArmSmcLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a SuperVisor Call (SVC) interface.
|
||||||
|
#
|
||||||
ArmSvcLib|Include/Library/ArmSvcLib.h
|
ArmSvcLib|Include/Library/ArmSvcLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a default exception handler.
|
||||||
|
#
|
||||||
|
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an interface to query miscellaneous OEM
|
||||||
|
# information.
|
||||||
|
#
|
||||||
|
OemMiscLib|Include/Library/OemMiscLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an OpTee interface.
|
||||||
|
#
|
||||||
OpteeLib|Include/Library/OpteeLib.h
|
OpteeLib|Include/Library/OpteeLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides a semihosting interface.
|
||||||
|
#
|
||||||
|
SemihostLib|Include/Library/SemihostLib.h
|
||||||
|
|
||||||
|
## @libraryclass Provides an interface for a StandaloneMm Mmu.
|
||||||
|
#
|
||||||
StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
|
StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
|
||||||
|
|
||||||
[Guids.common]
|
[Guids.common]
|
||||||
@@ -84,6 +137,13 @@
|
|||||||
# hardware coherency (i.e., no virtualization or cache coherent DMA)
|
# hardware coherency (i.e., no virtualization or cache coherent DMA)
|
||||||
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
|
gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
|
||||||
|
|
||||||
|
[PcdsFeatureFlag.AARCH64]
|
||||||
|
## Used to select method for requesting services from S-EL1.<BR><BR>
|
||||||
|
# TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.<BR>
|
||||||
|
# FALSE - Selects SVC calls for communication between S-EL0 and SPMC.<BR>
|
||||||
|
# @Prompt Enable FF-A support.
|
||||||
|
gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
|
||||||
|
|
||||||
[PcdsFixedAtBuild.common]
|
[PcdsFixedAtBuild.common]
|
||||||
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
|
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
|
||||||
|
|
||||||
@@ -115,6 +175,20 @@
|
|||||||
# The Primary Core is ClusterId[0] & CoreId[0]
|
# The Primary Core is ClusterId[0] & CoreId[0]
|
||||||
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
|
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
|
||||||
|
|
||||||
|
#
|
||||||
|
# SMBIOS PCDs
|
||||||
|
#
|
||||||
|
gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
|
||||||
|
gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
|
||||||
|
gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
|
||||||
|
gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
|
||||||
|
gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
|
||||||
|
gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
|
||||||
|
gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
|
||||||
|
gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
|
||||||
|
gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
|
||||||
|
gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
|
||||||
|
|
||||||
#
|
#
|
||||||
# ARM L2x0 PCDs
|
# ARM L2x0 PCDs
|
||||||
#
|
#
|
||||||
@@ -215,6 +289,9 @@
|
|||||||
gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
|
gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
|
||||||
gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
|
gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
|
||||||
|
|
||||||
|
gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
|
||||||
|
gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
|
||||||
|
|
||||||
[PcdsFixedAtBuild.common, PcdsDynamic.common]
|
[PcdsFixedAtBuild.common, PcdsDynamic.common]
|
||||||
#
|
#
|
||||||
# ARM Architectural Timer
|
# ARM Architectural Timer
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
# ARM processor package.
|
# ARM processor package.
|
||||||
#
|
#
|
||||||
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
# Copyright (c) 2011 - 2018, ARM Ltd. All rights reserved.<BR>
|
# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
|
# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
|
||||||
# Copyright (c) Microsoft Corporation.<BR>
|
# Copyright (c) Microsoft Corporation.<BR>
|
||||||
#
|
#
|
||||||
@@ -29,17 +29,25 @@
|
|||||||
RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
|
RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
|
||||||
*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
|
*_*_*_CC_FLAGS = -DDISABLE_NEW_DEPRECATED_INTERFACES
|
||||||
|
|
||||||
|
[PcdsFixedAtBuild]
|
||||||
|
gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
|
||||||
|
|
||||||
|
!include MdePkg/MdeLibs.dsc.inc
|
||||||
|
|
||||||
[LibraryClasses.common]
|
[LibraryClasses.common]
|
||||||
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
|
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
|
||||||
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
|
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
|
||||||
|
BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
|
||||||
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
|
CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
|
||||||
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
|
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
|
||||||
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
|
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
|
||||||
|
DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
|
||||||
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
|
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
|
||||||
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
|
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
|
||||||
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
|
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
|
||||||
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
|
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
|
||||||
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
|
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
|
||||||
|
UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
|
||||||
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
|
UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
|
||||||
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
|
UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
|
||||||
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
|
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
|
||||||
@@ -47,6 +55,7 @@
|
|||||||
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
|
UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
|
||||||
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
|
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
|
||||||
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
|
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
|
||||||
|
PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
|
||||||
|
|
||||||
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
|
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
|
||||||
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
|
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
|
||||||
@@ -81,6 +90,8 @@
|
|||||||
|
|
||||||
ArmMtlLib|ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
|
ArmMtlLib|ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.inf
|
||||||
|
|
||||||
|
OemMiscLib|ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
|
||||||
|
|
||||||
[LibraryClasses.common.PEIM]
|
[LibraryClasses.common.PEIM]
|
||||||
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
|
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
|
||||||
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
|
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
|
||||||
@@ -142,8 +153,12 @@
|
|||||||
|
|
||||||
ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
|
ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.inf
|
||||||
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
|
ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf
|
||||||
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
|
|
||||||
|
ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
|
||||||
|
ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
|
||||||
|
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLibNull.inf
|
||||||
|
|
||||||
[Components.AARCH64]
|
[Components.AARCH64]
|
||||||
|
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
|
||||||
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
|
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
|
||||||
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
|
ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
|
||||||
|
@@ -6,8 +6,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
|
|||||||
|
|
||||||
--*/
|
--*/
|
||||||
|
|
||||||
#ifndef __ARM_GIC_DXE_H__
|
#ifndef ARM_GIC_DXE_H_
|
||||||
#define __ARM_GIC_DXE_H__
|
#define ARM_GIC_DXE_H_
|
||||||
|
|
||||||
#include <Library/ArmGicLib.h>
|
#include <Library/ArmGicLib.h>
|
||||||
#include <Library/ArmLib.h>
|
#include <Library/ArmLib.h>
|
||||||
@@ -76,4 +76,4 @@ GicGetDistributorIcfgBaseAndBit (
|
|||||||
OUT UINTN *Config1Bit
|
OUT UINTN *Config1Bit
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_GIC_DXE_H_
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
*
|
*
|
||||||
* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
|
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
@@ -25,10 +25,13 @@
|
|||||||
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
|
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
|
||||||
|
|
||||||
#define ISENABLER_ADDRESS(base,offset) ((base) + \
|
#define ISENABLER_ADDRESS(base,offset) ((base) + \
|
||||||
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + (4 * offset))
|
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
|
||||||
|
|
||||||
#define ICENABLER_ADDRESS(base,offset) ((base) + \
|
#define ICENABLER_ADDRESS(base,offset) ((base) + \
|
||||||
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + (4 * offset))
|
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
|
||||||
|
|
||||||
|
#define IPRIORITY_ADDRESS(base,offset) ((base) + \
|
||||||
|
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
|
||||||
|
|
||||||
/**
|
/**
|
||||||
*
|
*
|
||||||
@@ -117,7 +120,14 @@ ArmGicGetMaxNumInterrupts (
|
|||||||
IN INTN GicDistributorBase
|
IN INTN GicDistributorBase
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
|
UINTN ItLines;
|
||||||
|
|
||||||
|
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Interrupt ID 1020-1023 are reserved.
|
||||||
|
//
|
||||||
|
return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
@@ -199,6 +209,50 @@ ArmGicEndOfInterrupt (
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
ArmGicSetInterruptPriority (
|
||||||
|
IN UINTN GicDistributorBase,
|
||||||
|
IN UINTN GicRedistributorBase,
|
||||||
|
IN UINTN Source,
|
||||||
|
IN UINTN Priority
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINT32 RegOffset;
|
||||||
|
UINTN RegShift;
|
||||||
|
ARM_GIC_ARCH_REVISION Revision;
|
||||||
|
UINTN GicCpuRedistributorBase;
|
||||||
|
|
||||||
|
// Calculate register offset and bit position
|
||||||
|
RegOffset = Source / 4;
|
||||||
|
RegShift = (Source % 4) * 8;
|
||||||
|
|
||||||
|
Revision = ArmGicGetSupportedArchRevision ();
|
||||||
|
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
||||||
|
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
|
||||||
|
SourceIsSpi (Source)) {
|
||||||
|
MmioAndThenOr32 (
|
||||||
|
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
|
||||||
|
~(0xff << RegShift),
|
||||||
|
Priority << RegShift
|
||||||
|
);
|
||||||
|
} else {
|
||||||
|
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
|
||||||
|
GicRedistributorBase,
|
||||||
|
Revision
|
||||||
|
);
|
||||||
|
if (GicCpuRedistributorBase == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
MmioAndThenOr32 (
|
||||||
|
IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),
|
||||||
|
~(0xff << RegShift),
|
||||||
|
Priority << RegShift
|
||||||
|
);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmGicEnableInterrupt (
|
ArmGicEnableInterrupt (
|
||||||
|
@@ -1,58 +0,0 @@
|
|||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Base.h>
|
|
||||||
#include <Library/DebugLib.h>
|
|
||||||
#include <Library/IoLib.h>
|
|
||||||
#include <Library/ArmGicLib.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function configures the interrupts set by the mask to be secure.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ArmGicSetSecureInterrupts (
|
|
||||||
IN UINTN GicDistributorBase,
|
|
||||||
IN UINTN* GicSecureInterruptMask,
|
|
||||||
IN UINTN GicSecureInterruptMaskSize
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINTN Index;
|
|
||||||
UINT32 InterruptStatus;
|
|
||||||
|
|
||||||
// We must not have more interrupts defined by the mask than the number of available interrupts
|
|
||||||
ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
|
|
||||||
|
|
||||||
// Set all the interrupts defined by the mask as Secure
|
|
||||||
for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
|
|
||||||
InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
|
|
||||||
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ArmGicEnableDistributor (
|
|
||||||
IN INTN GicDistributorBase
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Turn on the GIC distributor
|
|
||||||
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
VOID
|
|
||||||
EFIAPI
|
|
||||||
ArmGicSetupNonSecure (
|
|
||||||
IN UINTN MpId,
|
|
||||||
IN INTN GicDistributorBase,
|
|
||||||
IN INTN GicInterruptInterfaceBase
|
|
||||||
)
|
|
||||||
{
|
|
||||||
ArmGicV2SetupNonSecure (MpId, GicDistributorBase, GicInterruptInterfaceBase);
|
|
||||||
}
|
|
@@ -121,7 +121,7 @@ GicV2GetInterruptSourceState (
|
|||||||
@param This Instance pointer for this protocol
|
@param This Instance pointer for this protocol
|
||||||
@param Source Hardware source of the interrupt
|
@param Source Hardware source of the interrupt
|
||||||
|
|
||||||
@retval EFI_SUCCESS Source interrupt EOI'ed.
|
@retval EFI_SUCCESS Source interrupt ended successfully.
|
||||||
@retval EFI_UNSUPPORTED Source interrupt is not supported
|
@retval EFI_UNSUPPORTED Source interrupt is not supported
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
@@ -115,7 +115,7 @@ GicV3GetInterruptSourceState (
|
|||||||
@param This Instance pointer for this protocol
|
@param This Instance pointer for this protocol
|
||||||
@param Source Hardware source of the interrupt
|
@param Source Hardware source of the interrupt
|
||||||
|
|
||||||
@retval EFI_SUCCESS Source interrupt EOI'ed.
|
@retval EFI_SUCCESS Source interrupt ended successfully.
|
||||||
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
|
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
@@ -374,8 +374,6 @@ GicV3DxeInitialize (
|
|||||||
{
|
{
|
||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINTN Index;
|
UINTN Index;
|
||||||
UINT32 RegOffset;
|
|
||||||
UINTN RegShift;
|
|
||||||
UINT64 CpuTarget;
|
UINT64 CpuTarget;
|
||||||
UINT64 MpId;
|
UINT64 MpId;
|
||||||
|
|
||||||
@@ -397,12 +395,11 @@ GicV3DxeInitialize (
|
|||||||
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
|
GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index);
|
||||||
|
|
||||||
// Set Priority
|
// Set Priority
|
||||||
RegOffset = Index / 4;
|
ArmGicSetInterruptPriority (
|
||||||
RegShift = (Index % 4) * 8;
|
mGicDistributorBase,
|
||||||
MmioAndThenOr32 (
|
mGicRedistributorsBase,
|
||||||
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
|
Index,
|
||||||
~(0xff << RegShift),
|
ARM_GIC_DEFAULT_PRIORITY
|
||||||
ARM_GIC_DEFAULT_PRIORITY << RegShift
|
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
#/** @file
|
#/** @file
|
||||||
#
|
#
|
||||||
# Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
# Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
@@ -18,11 +18,16 @@
|
|||||||
ENTRY_POINT = ArmScmiDxeEntryPoint
|
ENTRY_POINT = ArmScmiDxeEntryPoint
|
||||||
|
|
||||||
[Sources.common]
|
[Sources.common]
|
||||||
Scmi.c
|
ArmScmiBaseProtocolPrivate.h
|
||||||
|
ArmScmiClockProtocolPrivate.h
|
||||||
|
ArmScmiPerformanceProtocolPrivate.h
|
||||||
ScmiBaseProtocol.c
|
ScmiBaseProtocol.c
|
||||||
|
Scmi.c
|
||||||
ScmiClockProtocol.c
|
ScmiClockProtocol.c
|
||||||
ScmiDxe.c
|
ScmiDxe.c
|
||||||
|
ScmiDxe.h
|
||||||
ScmiPerformanceProtocol.c
|
ScmiPerformanceProtocol.c
|
||||||
|
ScmiPrivate.h
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
ArmPkg/ArmPkg.dec
|
ArmPkg/ArmPkg.dec
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -22,7 +22,7 @@
|
|||||||
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
|
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
|
||||||
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
|
#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
|
||||||
|
|
||||||
/** Return values for SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS command.
|
/** Return values for ScmiMessageIdPerformanceDescribeLevels command.
|
||||||
SCMI Spec section 4.5.2.5
|
SCMI Spec section 4.5.2.5
|
||||||
**/
|
**/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -95,7 +95,7 @@ ScmiCommandExecute (
|
|||||||
// Fill in message header.
|
// Fill in message header.
|
||||||
MessageHeader = SCMI_MESSAGE_HEADER (
|
MessageHeader = SCMI_MESSAGE_HEADER (
|
||||||
Command->MessageId,
|
Command->MessageId,
|
||||||
SCMI_MESSAGE_TYPE_COMMAND,
|
ScmiMessageTypeCommand,
|
||||||
Command->ProtocolId
|
Command->ProtocolId
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -123,7 +123,7 @@ ScmiCommandExecute (
|
|||||||
|
|
||||||
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
|
Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
|
||||||
|
|
||||||
if (Response->Status != SCMI_SUCCESS) {
|
if (Response->Status != ScmiSuccess) {
|
||||||
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
|
DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
|
||||||
Command->ProtocolId,
|
Command->ProtocolId,
|
||||||
Command->MessageId,
|
Command->MessageId,
|
||||||
@@ -161,8 +161,9 @@ ScmiProtocolDiscoveryCommon (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
SCMI_COMMAND Command;
|
SCMI_COMMAND Command;
|
||||||
UINT32 PayloadLength = 0;
|
UINT32 PayloadLength;
|
||||||
|
|
||||||
|
PayloadLength = 0;
|
||||||
Command.ProtocolId = ProtocolId;
|
Command.ProtocolId = ProtocolId;
|
||||||
Command.MessageId = MessageId;
|
Command.MessageId = MessageId;
|
||||||
|
|
||||||
@@ -194,7 +195,7 @@ ScmiGetProtocolVersion (
|
|||||||
|
|
||||||
Status = ScmiProtocolDiscoveryCommon (
|
Status = ScmiProtocolDiscoveryCommon (
|
||||||
ProtocolId,
|
ProtocolId,
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_VERSION,
|
ScmiMessageIdProtocolVersion,
|
||||||
(UINT32**)&ProtocolVersion
|
(UINT32**)&ProtocolVersion
|
||||||
);
|
);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
@@ -223,7 +224,7 @@ ScmiGetProtocolAttributes (
|
|||||||
{
|
{
|
||||||
return ScmiProtocolDiscoveryCommon (
|
return ScmiProtocolDiscoveryCommon (
|
||||||
ProtocolId,
|
ProtocolId,
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES,
|
ScmiMessageIdProtocolAttributes,
|
||||||
ReturnValues
|
ReturnValues
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
@@ -245,7 +246,7 @@ ScmiGetProtocolMessageAttributes (
|
|||||||
{
|
{
|
||||||
return ScmiProtocolDiscoveryCommon (
|
return ScmiProtocolDiscoveryCommon (
|
||||||
ProtocolId,
|
ProtocolId,
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES,
|
ScmiMessageIdProtocolMessageAttributes,
|
||||||
ReturnValues
|
ReturnValues
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -34,7 +34,7 @@ BaseGetVersion (
|
|||||||
OUT UINT32 *Version
|
OUT UINT32 *Version
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_BASE, Version);
|
return ScmiGetProtocolVersion (ScmiProtocolIdBase, Version);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Return total number of SCMI protocols supported by the SCP firmware.
|
/** Return total number of SCMI protocols supported by the SCP firmware.
|
||||||
@@ -57,7 +57,7 @@ BaseGetTotalProtocols (
|
|||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINT32 *ReturnValues;
|
UINT32 *ReturnValues;
|
||||||
|
|
||||||
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_BASE, &ReturnValues);
|
Status = ScmiGetProtocolAttributes (ScmiProtocolIdBase, &ReturnValues);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
@@ -69,9 +69,9 @@ BaseGetTotalProtocols (
|
|||||||
|
|
||||||
/** Common function which returns vendor details.
|
/** Common function which returns vendor details.
|
||||||
|
|
||||||
@param[in] MessageId SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR
|
@param[in] MessageId ScmiMessageIdBaseDiscoverVendor
|
||||||
OR
|
OR
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR
|
ScmiMessageIdBaseDiscoverSubVendor
|
||||||
|
|
||||||
@param[out] VendorIdentifier ASCII name of the vendor/subvendor.
|
@param[out] VendorIdentifier ASCII name of the vendor/subvendor.
|
||||||
|
|
||||||
@@ -91,7 +91,7 @@ BaseDiscoverVendorDetails (
|
|||||||
SCMI_COMMAND Cmd;
|
SCMI_COMMAND Cmd;
|
||||||
UINT32 PayloadLength;
|
UINT32 PayloadLength;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
|
Cmd.ProtocolId = ScmiProtocolIdBase;
|
||||||
Cmd.MessageId = MessageId;
|
Cmd.MessageId = MessageId;
|
||||||
|
|
||||||
PayloadLength = 0;
|
PayloadLength = 0;
|
||||||
@@ -133,7 +133,7 @@ BaseDiscoverVendor (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
return BaseDiscoverVendorDetails (
|
return BaseDiscoverVendorDetails (
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR,
|
ScmiMessageIdBaseDiscoverVendor,
|
||||||
VendorIdentifier
|
VendorIdentifier
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
@@ -156,7 +156,7 @@ BaseDiscoverSubVendor (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
return BaseDiscoverVendorDetails (
|
return BaseDiscoverVendorDetails (
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR,
|
ScmiMessageIdBaseDiscoverSubVendor,
|
||||||
VendorIdentifier
|
VendorIdentifier
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
@@ -183,8 +183,8 @@ BaseDiscoverImplVersion (
|
|||||||
SCMI_COMMAND Cmd;
|
SCMI_COMMAND Cmd;
|
||||||
UINT32 PayloadLength;
|
UINT32 PayloadLength;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
|
Cmd.ProtocolId = ScmiProtocolIdBase;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION;
|
Cmd.MessageId = ScmiMessageIdBaseDiscoverImplementationVersion;
|
||||||
|
|
||||||
PayloadLength = 0;
|
PayloadLength = 0;
|
||||||
|
|
||||||
@@ -250,8 +250,8 @@ BaseDiscoverListProtocols (
|
|||||||
return EFI_BUFFER_TOO_SMALL;
|
return EFI_BUFFER_TOO_SMALL;
|
||||||
}
|
}
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_BASE;
|
Cmd.ProtocolId = ScmiProtocolIdBase;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS;
|
Cmd.MessageId = ScmiMessageIdBaseDiscoverListProtocols;
|
||||||
|
|
||||||
Skip = 0;
|
Skip = 0;
|
||||||
|
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -52,7 +52,7 @@ ClockGetVersion (
|
|||||||
OUT UINT32 *Version
|
OUT UINT32 *Version
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_CLOCK, Version);
|
return ScmiGetProtocolVersion (ScmiProtocolIdClock, Version);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Return total number of clock devices supported by the clock management
|
/** Return total number of clock devices supported by the clock management
|
||||||
@@ -76,7 +76,7 @@ ClockGetTotalClocks (
|
|||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINT32 *ReturnValues;
|
UINT32 *ReturnValues;
|
||||||
|
|
||||||
Status = ScmiGetProtocolAttributes (SCMI_PROTOCOL_ID_CLOCK, &ReturnValues);
|
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
@@ -122,8 +122,8 @@ ClockGetClockAttributes (
|
|||||||
|
|
||||||
*MessageParams = ClockId;
|
*MessageParams = ClockId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
|
Cmd.ProtocolId = ScmiProtocolIdClock;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES;
|
Cmd.MessageId = ScmiMessageIdClockAttributes;
|
||||||
|
|
||||||
PayloadLength = sizeof (ClockId);
|
PayloadLength = sizeof (ClockId);
|
||||||
|
|
||||||
@@ -152,10 +152,10 @@ ClockGetClockAttributes (
|
|||||||
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
|
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
|
||||||
@param[in] ClockId Identifier for the clock device.
|
@param[in] ClockId Identifier for the clock device.
|
||||||
|
|
||||||
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
|
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
|
||||||
supports range of clock rates which are non-linear.
|
supports range of clock rates which are non-linear.
|
||||||
|
|
||||||
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
|
ScmiClockRateFormatLinear: Clock device supports
|
||||||
range of linear clock rates from Min to Max in steps.
|
range of linear clock rates from Min to Max in steps.
|
||||||
|
|
||||||
@param[out] TotalRates Total number of rates.
|
@param[out] TotalRates Total number of rates.
|
||||||
@@ -189,20 +189,22 @@ ClockDescribeRates (
|
|||||||
CLOCK_DESCRIBE_RATES *DescribeRates;
|
CLOCK_DESCRIBE_RATES *DescribeRates;
|
||||||
CLOCK_RATE_DWORD *Rate;
|
CLOCK_RATE_DWORD *Rate;
|
||||||
|
|
||||||
UINT32 RequiredArraySize = 0;
|
UINT32 RequiredArraySize;
|
||||||
UINT32 RateIndex = 0;
|
UINT32 RateIndex;
|
||||||
UINT32 RateNo;
|
UINT32 RateNo;
|
||||||
UINT32 RateOffset;
|
UINT32 RateOffset;
|
||||||
|
|
||||||
*TotalRates = 0;
|
*TotalRates = 0;
|
||||||
|
RequiredArraySize = 0;
|
||||||
|
RateIndex = 0;
|
||||||
|
|
||||||
Status = ScmiCommandGetPayload (&MessageParams);
|
Status = ScmiCommandGetPayload (&MessageParams);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
|
Cmd.ProtocolId = ScmiProtocolIdClock;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES;
|
Cmd.MessageId = ScmiMessageIdClockDescribeRates;
|
||||||
|
|
||||||
*MessageParams++ = ClockId;
|
*MessageParams++ = ClockId;
|
||||||
|
|
||||||
@@ -234,7 +236,7 @@ ClockDescribeRates (
|
|||||||
*TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
|
*TotalRates = NUM_RATES (DescribeRates->NumRatesFlags)
|
||||||
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
|
+ NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
|
||||||
|
|
||||||
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
|
if (*Format == ScmiClockRateFormatDiscrete) {
|
||||||
RequiredArraySize = (*TotalRates) * sizeof (UINT64);
|
RequiredArraySize = (*TotalRates) * sizeof (UINT64);
|
||||||
} else {
|
} else {
|
||||||
// We need to return triplet of 64 bit value for each rate
|
// We need to return triplet of 64 bit value for each rate
|
||||||
@@ -249,26 +251,30 @@ ClockDescribeRates (
|
|||||||
|
|
||||||
RateOffset = 0;
|
RateOffset = 0;
|
||||||
|
|
||||||
if (*Format == SCMI_CLOCK_RATE_FORMAT_DISCRETE) {
|
if (*Format == ScmiClockRateFormatDiscrete) {
|
||||||
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
|
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
|
||||||
Rate = &DescribeRates->Rates[RateOffset++];
|
Rate = &DescribeRates->Rates[RateOffset++];
|
||||||
// Non-linear discrete rates.
|
// Non-linear discrete rates.
|
||||||
RateArray[RateIndex++].Rate = ConvertTo64Bit (Rate->Low, Rate->High);
|
RateArray[RateIndex++].DiscreteRate.Rate =
|
||||||
|
ConvertTo64Bit (Rate->Low, Rate->High);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
|
for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
|
||||||
// Linear clock rates from minimum to maximum in steps
|
// Linear clock rates from minimum to maximum in steps
|
||||||
// Minimum clock rate.
|
// Minimum clock rate.
|
||||||
Rate = &DescribeRates->Rates[RateOffset++];
|
Rate = &DescribeRates->Rates[RateOffset++];
|
||||||
RateArray[RateIndex].Min = ConvertTo64Bit (Rate->Low, Rate->High);
|
RateArray[RateIndex].ContinuousRate.Min =
|
||||||
|
ConvertTo64Bit (Rate->Low, Rate->High);
|
||||||
|
|
||||||
Rate = &DescribeRates->Rates[RateOffset++];
|
Rate = &DescribeRates->Rates[RateOffset++];
|
||||||
// Maximum clock rate.
|
// Maximum clock rate.
|
||||||
RateArray[RateIndex].Max = ConvertTo64Bit (Rate->Low, Rate->High);
|
RateArray[RateIndex].ContinuousRate.Max =
|
||||||
|
ConvertTo64Bit (Rate->Low, Rate->High);
|
||||||
|
|
||||||
Rate = &DescribeRates->Rates[RateOffset++];
|
Rate = &DescribeRates->Rates[RateOffset++];
|
||||||
// Step.
|
// Step.
|
||||||
RateArray[RateIndex++].Step = ConvertTo64Bit (Rate->Low, Rate->High);
|
RateArray[RateIndex++].ContinuousRate.Step =
|
||||||
|
ConvertTo64Bit (Rate->Low, Rate->High);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
|
} while (NUM_REMAIN_RATES (DescribeRates->NumRatesFlags) != 0);
|
||||||
@@ -314,8 +320,8 @@ ClockRateGet (
|
|||||||
// Fill arguments for clock protocol command.
|
// Fill arguments for clock protocol command.
|
||||||
*MessageParams = ClockId;
|
*MessageParams = ClockId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
|
Cmd.ProtocolId = ScmiProtocolIdClock;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_GET;
|
Cmd.MessageId = ScmiMessageIdClockRateGet;
|
||||||
|
|
||||||
PayloadLength = sizeof (ClockId);
|
PayloadLength = sizeof (ClockId);
|
||||||
|
|
||||||
@@ -368,8 +374,8 @@ ClockRateSet (
|
|||||||
ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
|
ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
|
||||||
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
|
ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
|
Cmd.ProtocolId = ScmiProtocolIdClock;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_RATE_SET;
|
Cmd.MessageId = ScmiMessageIdClockRateSet;
|
||||||
|
|
||||||
PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
|
PayloadLength = sizeof (CLOCK_RATE_SET_ATTRIBUTES);
|
||||||
|
|
||||||
@@ -415,8 +421,8 @@ ClockEnable (
|
|||||||
ClockConfigSetAttributes->ClockId = ClockId;
|
ClockConfigSetAttributes->ClockId = ClockId;
|
||||||
ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
|
ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK;
|
Cmd.ProtocolId = ScmiProtocolIdClock;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET;
|
Cmd.MessageId = ScmiMessageIdClockConfigSet;
|
||||||
|
|
||||||
PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);
|
PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES);
|
||||||
|
|
||||||
|
@@ -1,12 +1,12 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
System Control and Management Interface V1.0
|
@par Specification Reference:
|
||||||
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
|
- Arm System Control and Management Interface - Platform Design Document
|
||||||
DEN0056A_System_Control_and_Management_Interface.pdf
|
(https://developer.arm.com/documentation/den0056/)
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#include <Base.h>
|
#include <Base.h>
|
||||||
@@ -24,9 +24,9 @@
|
|||||||
#include "ScmiPrivate.h"
|
#include "ScmiPrivate.h"
|
||||||
|
|
||||||
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
|
STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
|
||||||
{ SCMI_PROTOCOL_ID_BASE, ScmiBaseProtocolInit },
|
{ ScmiProtocolIdBase, ScmiBaseProtocolInit },
|
||||||
{ SCMI_PROTOCOL_ID_PERFORMANCE, ScmiPerformanceProtocolInit },
|
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
|
||||||
{ SCMI_PROTOCOL_ID_CLOCK, ScmiClockProtocolInit }
|
{ ScmiProtocolIdClock, ScmiClockProtocolInit }
|
||||||
};
|
};
|
||||||
|
|
||||||
/** ARM SCMI driver entry point function.
|
/** ARM SCMI driver entry point function.
|
||||||
@@ -61,7 +61,7 @@ ArmScmiDxeEntryPoint (
|
|||||||
UINT32 SupportedListSize;
|
UINT32 SupportedListSize;
|
||||||
|
|
||||||
// Every SCMI implementation must implement the base protocol.
|
// Every SCMI implementation must implement the base protocol.
|
||||||
ASSERT (Protocols[0].Id == SCMI_PROTOCOL_ID_BASE);
|
ASSERT (Protocols[0].Id == ScmiProtocolIdBase);
|
||||||
|
|
||||||
Status = ScmiBaseProtocolInit (&ImageHandle);
|
Status = ScmiBaseProtocolInit (&ImageHandle);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
@@ -86,7 +86,9 @@ ArmScmiDxeEntryPoint (
|
|||||||
return Status;
|
return Status;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (Version != BASE_PROTOCOL_VERSION) {
|
// Accept any version between SCMI v1.0 and SCMI v2.0
|
||||||
|
if ((Version < BASE_PROTOCOL_VERSION_V1) ||
|
||||||
|
(Version > BASE_PROTOCOL_VERSION_V2)) {
|
||||||
ASSERT (FALSE);
|
ASSERT (FALSE);
|
||||||
return EFI_UNSUPPORTED;
|
return EFI_UNSUPPORTED;
|
||||||
}
|
}
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -35,7 +35,7 @@ PerformanceGetVersion (
|
|||||||
OUT UINT32 *Version
|
OUT UINT32 *Version
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
return ScmiGetProtocolVersion (SCMI_PROTOCOL_ID_PERFORMANCE, Version);
|
return ScmiGetProtocolVersion (ScmiProtocolIdPerformance, Version);
|
||||||
}
|
}
|
||||||
|
|
||||||
/** Return protocol attributes of the performance management protocol.
|
/** Return protocol attributes of the performance management protocol.
|
||||||
@@ -59,7 +59,7 @@ PerformanceGetAttributes (
|
|||||||
UINT32* ReturnValues;
|
UINT32* ReturnValues;
|
||||||
|
|
||||||
Status = ScmiGetProtocolAttributes (
|
Status = ScmiGetProtocolAttributes (
|
||||||
SCMI_PROTOCOL_ID_PERFORMANCE,
|
ScmiProtocolIdPerformance,
|
||||||
&ReturnValues
|
&ReturnValues
|
||||||
);
|
);
|
||||||
if (EFI_ERROR (Status)) {
|
if (EFI_ERROR (Status)) {
|
||||||
@@ -107,8 +107,8 @@ PerformanceDomainAttributes (
|
|||||||
|
|
||||||
*MessageParams = DomainId;
|
*MessageParams = DomainId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES;
|
Cmd.MessageId = ScmiMessageIdPerformanceDomainAttributes;
|
||||||
|
|
||||||
PayloadLength = sizeof (DomainId);
|
PayloadLength = sizeof (DomainId);
|
||||||
|
|
||||||
@@ -179,8 +179,8 @@ PerformanceDescribeLevels (
|
|||||||
|
|
||||||
*MessageParams++ = DomainId;
|
*MessageParams++ = DomainId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS;
|
Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
|
||||||
|
|
||||||
do {
|
do {
|
||||||
|
|
||||||
@@ -258,8 +258,8 @@ PerformanceLimitsSet (
|
|||||||
*MessageParams++ = Limits->RangeMax;
|
*MessageParams++ = Limits->RangeMax;
|
||||||
*MessageParams = Limits->RangeMin;
|
*MessageParams = Limits->RangeMin;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET;
|
Cmd.MessageId = ScmiMessageIdPerformanceLimitsSet;
|
||||||
|
|
||||||
PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
|
PayloadLength = sizeof (DomainId) + sizeof (SCMI_PERFORMANCE_LIMITS);
|
||||||
|
|
||||||
@@ -304,8 +304,8 @@ PerformanceLimitsGet (
|
|||||||
|
|
||||||
*MessageParams = DomainId;
|
*MessageParams = DomainId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET;
|
Cmd.MessageId = ScmiMessageIdPerformanceLimitsGet;
|
||||||
|
|
||||||
PayloadLength = sizeof (DomainId);
|
PayloadLength = sizeof (DomainId);
|
||||||
|
|
||||||
@@ -354,8 +354,8 @@ PerformanceLevelSet (
|
|||||||
*MessageParams++ = DomainId;
|
*MessageParams++ = DomainId;
|
||||||
*MessageParams = Level;
|
*MessageParams = Level;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET;
|
Cmd.MessageId = ScmiMessageIdPerformanceLevelSet;
|
||||||
|
|
||||||
PayloadLength = sizeof (DomainId) + sizeof (Level);
|
PayloadLength = sizeof (DomainId) + sizeof (Level);
|
||||||
|
|
||||||
@@ -399,8 +399,8 @@ PerformanceLevelGet (
|
|||||||
|
|
||||||
*MessageParams = DomainId;
|
*MessageParams = DomainId;
|
||||||
|
|
||||||
Cmd.ProtocolId = SCMI_PROTOCOL_ID_PERFORMANCE;
|
Cmd.ProtocolId = ScmiProtocolIdPerformance;
|
||||||
Cmd.MessageId = SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET;
|
Cmd.MessageId = ScmiMessageIdPerformanceLevelGet;
|
||||||
|
|
||||||
PayloadLength = sizeof (DomainId);
|
PayloadLength = sizeof (DomainId);
|
||||||
|
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -13,41 +13,41 @@
|
|||||||
|
|
||||||
// SCMI protocol IDs.
|
// SCMI protocol IDs.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_PROTOCOL_ID_BASE = 0x10,
|
ScmiProtocolIdBase = 0x10,
|
||||||
SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11,
|
ScmiProtocolIdPowerDomain = 0x11,
|
||||||
SCMI_PROTOCOL_ID_SYSTEM_POWER = 0x12,
|
ScmiProtocolIdSystemPower = 0x12,
|
||||||
SCMI_PROTOCOL_ID_PERFORMANCE = 0x13,
|
ScmiProtocolIdPerformance = 0x13,
|
||||||
SCMI_PROTOCOL_ID_CLOCK = 0x14,
|
ScmiProtocolIdClock = 0x14,
|
||||||
SCMI_PROTOCOL_ID_SENSOR = 0x15
|
ScmiProtocolIdSensor = 0x15
|
||||||
} SCMI_PROTOCOL_ID;
|
} SCMI_PROTOCOL_ID;
|
||||||
|
|
||||||
// SCMI message types.
|
// SCMI message types.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_MESSAGE_TYPE_COMMAND = 0,
|
ScmiMessageTypeCommand = 0,
|
||||||
SCMI_MESSAGE_TYPE_DELAYED_RESPONSE = 2, // Skipping 1 is deliberate.
|
ScmiMessageTypeDelayedResponse = 2, // Skipping 1 is deliberate.
|
||||||
SCMI_MESSAGE_TYPE_NOTIFICATION = 3
|
ScmiMessageTypeNotification = 3
|
||||||
} SCMI_MESSAGE_TYPE;
|
} SCMI_MESSAGE_TYPE;
|
||||||
|
|
||||||
// SCMI response error codes.
|
// SCMI response error codes.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_SUCCESS = 0,
|
ScmiSuccess = 0,
|
||||||
SCMI_NOT_SUPPORTED = -1,
|
ScmiNotSupported = -1,
|
||||||
SCMI_INVALID_PARAMETERS = -2,
|
ScmiInvalidParameters = -2,
|
||||||
SCMI_DENIED = -3,
|
ScmiDenied = -3,
|
||||||
SCMI_NOT_FOUND = -4,
|
ScmiNotFound = -4,
|
||||||
SCMI_OUT_OF_RANGE = -5,
|
ScmiOutOfRange = -5,
|
||||||
SCMI_BUSY = -6,
|
ScmiBusy = -6,
|
||||||
SCMI_COMMS_ERROR = -7,
|
ScmiCommsError = -7,
|
||||||
SCMI_GENERIC_ERROR = -8,
|
ScmiGenericError = -8,
|
||||||
SCMI_HARDWARE_ERROR = -9,
|
ScmiHardwareError = -9,
|
||||||
SCMI_PROTOCOL_ERROR = -10
|
ScmiProtocolError = -10
|
||||||
} SCMI_STATUS;
|
} SCMI_STATUS;
|
||||||
|
|
||||||
// SCMI message IDs common to all protocols.
|
// SCMI message IDs common to all protocols.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_VERSION = 0x0,
|
ScmiMessageIdProtocolVersion = 0x0,
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_ATTRIBUTES = 0x1,
|
ScmiMessageIdProtocolAttributes = 0x1,
|
||||||
SCMI_MESSAGE_ID_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2
|
ScmiMessageIdProtocolMessageAttributes = 0x2
|
||||||
} SCMI_MESSAGE_ID;
|
} SCMI_MESSAGE_ID;
|
||||||
|
|
||||||
// Not defined in SCMI specification but will help to identify a message.
|
// Not defined in SCMI specification but will help to identify a message.
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
|
|
||||||
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
|
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
|
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
|
Portions copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
@@ -189,7 +189,7 @@ SyncCacheConfig (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINT32 PageAttribute = 0;
|
UINT32 PageAttribute;
|
||||||
UINT64 *FirstLevelTableAddress;
|
UINT64 *FirstLevelTableAddress;
|
||||||
UINTN TableLevel;
|
UINTN TableLevel;
|
||||||
UINTN TableCount;
|
UINTN TableCount;
|
||||||
@@ -282,12 +282,12 @@ EfiAttributeToArmAttribute (
|
|||||||
ArmAttributes |= TT_AF;
|
ArmAttributes |= TT_AF;
|
||||||
|
|
||||||
// Determine protection attributes
|
// Determine protection attributes
|
||||||
if (EfiAttributes & EFI_MEMORY_RO) {
|
if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
|
||||||
ArmAttributes |= TT_AP_RO_RO;
|
ArmAttributes |= TT_AP_RO_RO;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Process eXecute Never attribute
|
// Process eXecute Never attribute
|
||||||
if (EfiAttributes & EFI_MEMORY_XP) {
|
if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
|
||||||
ArmAttributes |= TT_PXN_MASK;
|
ArmAttributes |= TT_PXN_MASK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
|
|
||||||
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
|
Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
|
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
|
Portions copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
|
||||||
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
@@ -155,8 +155,8 @@ SyncCacheConfigPage (
|
|||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINT32 i;
|
UINT32 i;
|
||||||
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
|
volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
|
||||||
UINT32 NextPageAttributes = 0;
|
UINT32 NextPageAttributes;
|
||||||
UINT32 PageAttributes = 0;
|
UINT32 PageAttributes;
|
||||||
UINT32 BaseAddress;
|
UINT32 BaseAddress;
|
||||||
UINT64 GcdAttributes;
|
UINT64 GcdAttributes;
|
||||||
|
|
||||||
@@ -226,8 +226,8 @@ SyncCacheConfig (
|
|||||||
UINT32 i;
|
UINT32 i;
|
||||||
EFI_PHYSICAL_ADDRESS NextRegionBase;
|
EFI_PHYSICAL_ADDRESS NextRegionBase;
|
||||||
UINT64 NextRegionLength;
|
UINT64 NextRegionLength;
|
||||||
UINT32 NextSectionAttributes = 0;
|
UINT32 NextSectionAttributes;
|
||||||
UINT32 SectionAttributes = 0;
|
UINT32 SectionAttributes;
|
||||||
UINT64 GcdAttributes;
|
UINT64 GcdAttributes;
|
||||||
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
|
volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
|
||||||
UINTN NumberOfDescriptors;
|
UINTN NumberOfDescriptors;
|
||||||
@@ -345,7 +345,7 @@ EfiAttributeToArmAttribute (
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case EFI_MEMORY_WC:
|
case EFI_MEMORY_WC:
|
||||||
// Map to normal non-cachable
|
// Map to normal non-cacheable
|
||||||
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
|
ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@@ -366,14 +366,14 @@ EfiAttributeToArmAttribute (
|
|||||||
}
|
}
|
||||||
|
|
||||||
// Determine protection attributes
|
// Determine protection attributes
|
||||||
if (EfiAttributes & EFI_MEMORY_RO) {
|
if ((EfiAttributes & EFI_MEMORY_RO) != 0) {
|
||||||
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
|
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
|
||||||
} else {
|
} else {
|
||||||
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
|
ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Determine eXecute Never attribute
|
// Determine eXecute Never attribute
|
||||||
if (EfiAttributes & EFI_MEMORY_XP) {
|
if ((EfiAttributes & EFI_MEMORY_XP) != 0) {
|
||||||
ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
|
ArmAttributes |= TT_DESCRIPTOR_SECTION_XN_MASK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -7,8 +7,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __CPU_DXE_ARM_EXCEPTION_H__
|
#ifndef CPU_DXE_H_
|
||||||
#define __CPU_DXE_ARM_EXCEPTION_H__
|
#define CPU_DXE_H_
|
||||||
|
|
||||||
#include <Uefi.h>
|
#include <Uefi.h>
|
||||||
|
|
||||||
@@ -143,4 +143,4 @@ SetGcdMemorySpaceAttributes (
|
|||||||
IN UINT64 Attributes
|
IN UINT64 Attributes
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __CPU_DXE_ARM_EXCEPTION_H__
|
#endif // CPU_DXE_H_
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
*
|
*
|
||||||
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
|
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
@@ -32,7 +32,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
/** Publish ARM Processor Data table in UEFI SYSTEM Table.
|
/** Publish ARM Processor Data table in UEFI SYSTEM Table.
|
||||||
* @param: HobStart Pointer to the beginning of the HOB List from PEI.
|
* @param HobStart Pointer to the beginning of the HOB List from PEI.
|
||||||
*
|
*
|
||||||
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
|
* Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.
|
||||||
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
|
* If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory
|
||||||
|
@@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
|
Portions Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -14,7 +14,8 @@
|
|||||||
EFI_STATUS
|
EFI_STATUS
|
||||||
InitializeExceptions (
|
InitializeExceptions (
|
||||||
IN EFI_CPU_ARCH_PROTOCOL *Cpu
|
IN EFI_CPU_ARCH_PROTOCOL *Cpu
|
||||||
) {
|
)
|
||||||
|
{
|
||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
|
EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
|
||||||
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
|
EFI_VECTOR_HANDOFF_INFO *VectorInfo;
|
||||||
@@ -92,7 +93,8 @@ EFI_STATUS
|
|||||||
RegisterInterruptHandler(
|
RegisterInterruptHandler(
|
||||||
IN EFI_EXCEPTION_TYPE InterruptType,
|
IN EFI_EXCEPTION_TYPE InterruptType,
|
||||||
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
|
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
|
||||||
) {
|
)
|
||||||
|
{
|
||||||
// pass down to CpuExceptionHandlerLib
|
// pass down to CpuExceptionHandlerLib
|
||||||
return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
|
return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
|
||||||
}
|
}
|
||||||
|
@@ -5,8 +5,8 @@
|
|||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
#ifndef __GENERIC_WATCHDOG_H__
|
#ifndef GENERIC_WATCHDOG_H_
|
||||||
#define __GENERIC_WATCHDOG_H__
|
#define GENERIC_WATCHDOG_H_
|
||||||
|
|
||||||
// Refresh Frame:
|
// Refresh Frame:
|
||||||
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
|
#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
|
||||||
@@ -21,4 +21,4 @@
|
|||||||
#define GENERIC_WDOG_ENABLED 1
|
#define GENERIC_WDOG_ENABLED 1
|
||||||
#define GENERIC_WDOG_DISABLED 0
|
#define GENERIC_WDOG_DISABLED 0
|
||||||
|
|
||||||
#endif // __GENERIC_WATCHDOG_H__
|
#endif // GENERIC_WATCHDOG_H_
|
||||||
|
@@ -1,5 +1,5 @@
|
|||||||
#
|
#
|
||||||
# Copyright (c) 2013-2017, ARM Limited. All rights reserved.
|
# Copyright (c) 2013-2021, Arm Limited. All rights reserved.<BR>
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
@@ -13,6 +13,7 @@
|
|||||||
ENTRY_POINT = GenericWatchdogEntry
|
ENTRY_POINT = GenericWatchdogEntry
|
||||||
|
|
||||||
[Sources.common]
|
[Sources.common]
|
||||||
|
GenericWatchdog.h
|
||||||
GenericWatchdogDxe.c
|
GenericWatchdogDxe.c
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
|
@@ -1,13 +1,13 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2016-2018, ARM Limited. All rights reserved.
|
Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#if !defined _MM_COMMUNICATE_H_
|
#ifndef MM_COMMUNICATE_H_
|
||||||
#define _MM_COMMUNICATE_H_
|
#define MM_COMMUNICATE_H_
|
||||||
|
|
||||||
#define MM_MAJOR_VER_MASK 0xEFFF0000
|
#define MM_MAJOR_VER_MASK 0xEFFF0000
|
||||||
#define MM_MINOR_VER_MASK 0x0000FFFF
|
#define MM_MINOR_VER_MASK 0x0000FFFF
|
||||||
@@ -19,4 +19,4 @@
|
|||||||
#define MM_CALLER_MAJOR_VER 0x1UL
|
#define MM_CALLER_MAJOR_VER 0x1UL
|
||||||
#define MM_CALLER_MINOR_VER 0x0
|
#define MM_CALLER_MINOR_VER 0x0
|
||||||
|
|
||||||
#endif /* _MM_COMMUNICATE_H_ */
|
#endif /* MM_COMMUNICATE_H_ */
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2016-2019, ARM Limited. All rights reserved.
|
Copyright (c) 2016-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -96,7 +96,7 @@ MmCommunication2Communicate (
|
|||||||
sizeof (CommunicateHeader->MessageLength);
|
sizeof (CommunicateHeader->MessageLength);
|
||||||
|
|
||||||
// If the length of the CommBuffer is 0 then return the expected length.
|
// If the length of the CommBuffer is 0 then return the expected length.
|
||||||
if (CommSize) {
|
if (CommSize != 0) {
|
||||||
// This case can be used by the consumer of this driver to find out the
|
// This case can be used by the consumer of this driver to find out the
|
||||||
// max size that can be used for allocating CommBuffer.
|
// max size that can be used for allocating CommBuffer.
|
||||||
if ((*CommSize == 0) ||
|
if ((*CommSize == 0) ||
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
#
|
#
|
||||||
# DXE MM Communicate driver
|
# DXE MM Communicate driver
|
||||||
#
|
#
|
||||||
# Copyright (c) 2016 - 2019, ARM Limited. All rights reserved.
|
# Copyright (c) 2016 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
@@ -24,6 +24,7 @@
|
|||||||
#
|
#
|
||||||
|
|
||||||
[Sources.AARCH64]
|
[Sources.AARCH64]
|
||||||
|
MmCommunicate.h
|
||||||
MmCommunication.c
|
MmCommunication.c
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
|
@@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
Timer Architecture Protocol driver of the ARM flavor
|
Timer Architecture Protocol driver of the ARM flavor
|
||||||
|
|
||||||
Copyright (c) 2011-2013 ARM Ltd. All rights reserved.<BR>
|
Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -307,7 +307,7 @@ TimerInterruptHandler (
|
|||||||
// Check if the timer interrupt is active
|
// Check if the timer interrupt is active
|
||||||
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
|
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
|
||||||
|
|
||||||
if (mTimerNotifyFunction) {
|
if (mTimerNotifyFunction != 0) {
|
||||||
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
|
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -359,7 +359,7 @@ TimerInitialize (
|
|||||||
IN EFI_SYSTEM_TABLE *SystemTable
|
IN EFI_SYSTEM_TABLE *SystemTable
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
EFI_HANDLE Handle = NULL;
|
EFI_HANDLE Handle;
|
||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINTN TimerCtrlReg;
|
UINTN TimerCtrlReg;
|
||||||
UINT32 TimerHypIntrNum;
|
UINT32 TimerHypIntrNum;
|
||||||
@@ -408,6 +408,7 @@ TimerInitialize (
|
|||||||
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
|
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
|
||||||
ASSERT_EFI_ERROR (Status);
|
ASSERT_EFI_ERROR (Status);
|
||||||
|
|
||||||
|
Handle = NULL;
|
||||||
// Install the Timer Architectural Protocol onto a new handle
|
// Install the Timer Architectural Protocol onto a new handle
|
||||||
Status = gBS->InstallMultipleProtocolInterfaces(
|
Status = gBS->InstallMultipleProtocolInterfaces(
|
||||||
&Handle,
|
&Handle,
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
Support a Semi Host file system over a debuggers JTAG
|
Support a Semi Host file system over a debuggers JTAG
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
|
Portions copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -51,7 +51,7 @@ EFI_FILE gSemihostFsFile = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
//
|
//
|
||||||
// Device path for semi-hosting. It contains our autogened Caller ID GUID.
|
// Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
|
||||||
//
|
//
|
||||||
typedef struct {
|
typedef struct {
|
||||||
VENDOR_DEVICE_PATH Guid;
|
VENDOR_DEVICE_PATH Guid;
|
||||||
@@ -90,8 +90,9 @@ AllocateFCB (
|
|||||||
VOID
|
VOID
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
|
SEMIHOST_FCB *Fcb;
|
||||||
|
|
||||||
|
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
|
||||||
if (Fcb != NULL) {
|
if (Fcb != NULL) {
|
||||||
CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));
|
CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));
|
||||||
Fcb->Signature = SEMIHOST_FCB_SIGNATURE;
|
Fcb->Signature = SEMIHOST_FCB_SIGNATURE;
|
||||||
@@ -122,7 +123,7 @@ VolumeOpen (
|
|||||||
OUT EFI_FILE **Root
|
OUT EFI_FILE **Root
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
SEMIHOST_FCB *RootFcb = NULL;
|
SEMIHOST_FCB *RootFcb;
|
||||||
|
|
||||||
if (Root == NULL) {
|
if (Root == NULL) {
|
||||||
return EFI_INVALID_PARAMETER;
|
return EFI_INVALID_PARAMETER;
|
||||||
@@ -196,8 +197,8 @@ FileOpen (
|
|||||||
return EFI_INVALID_PARAMETER;
|
return EFI_INVALID_PARAMETER;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((OpenMode & EFI_FILE_MODE_CREATE) &&
|
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
|
||||||
(Attributes & EFI_FILE_DIRECTORY) ) {
|
((Attributes & EFI_FILE_DIRECTORY) != 0)) {
|
||||||
return EFI_WRITE_PROTECTED;
|
return EFI_WRITE_PROTECTED;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -234,7 +235,7 @@ FileOpen (
|
|||||||
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
|
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
|
||||||
|
|
||||||
if (RETURN_ERROR (Return)) {
|
if (RETURN_ERROR (Return)) {
|
||||||
if (OpenMode & EFI_FILE_MODE_CREATE) {
|
if ((OpenMode & EFI_FILE_MODE_CREATE) != 0) {
|
||||||
//
|
//
|
||||||
// In the create if does not exist case, if the opening in update
|
// In the create if does not exist case, if the opening in update
|
||||||
// mode failed, create it and open it in update mode. The update
|
// mode failed, create it and open it in update mode. The update
|
||||||
@@ -277,7 +278,8 @@ FileOpen (
|
|||||||
|
|
||||||
FileFcb->Info.FileSize = Length;
|
FileFcb->Info.FileSize = Length;
|
||||||
FileFcb->Info.PhysicalSize = Length;
|
FileFcb->Info.PhysicalSize = Length;
|
||||||
FileFcb->Info.Attribute = (OpenMode & EFI_FILE_MODE_CREATE) ? Attributes : 0;
|
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
|
||||||
|
Attributes : 0;
|
||||||
|
|
||||||
InsertTailList (&gFileList, &FileFcb->Link);
|
InsertTailList (&gFileList, &FileFcb->Link);
|
||||||
|
|
||||||
@@ -758,12 +760,13 @@ GetFileInfo (
|
|||||||
OUT VOID *Buffer
|
OUT VOID *Buffer
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
EFI_FILE_INFO *Info = NULL;
|
EFI_FILE_INFO *Info;
|
||||||
UINTN NameSize = 0;
|
UINTN NameSize;
|
||||||
UINTN ResultSize;
|
UINTN ResultSize;
|
||||||
UINTN Index;
|
UINTN Index;
|
||||||
|
|
||||||
if (Fcb->IsRoot == TRUE) {
|
if (Fcb->IsRoot) {
|
||||||
|
NameSize = 0;
|
||||||
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
|
ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
|
||||||
} else {
|
} else {
|
||||||
NameSize = AsciiStrLen (Fcb->FileName) + 1;
|
NameSize = AsciiStrLen (Fcb->FileName) + 1;
|
||||||
@@ -783,7 +786,7 @@ GetFileInfo (
|
|||||||
// Fill in the structure
|
// Fill in the structure
|
||||||
Info->Size = ResultSize;
|
Info->Size = ResultSize;
|
||||||
|
|
||||||
if (Fcb->IsRoot == TRUE) {
|
if (Fcb->IsRoot) {
|
||||||
Info->FileName[0] = L'\0';
|
Info->FileName[0] = L'\0';
|
||||||
} else {
|
} else {
|
||||||
for (Index = 0; Index < NameSize; Index++) {
|
for (Index = 0; Index < NameSize; Index++) {
|
||||||
|
@@ -7,8 +7,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __SEMIHOST_FS_H__
|
#ifndef SEMIHOST_FS_H_
|
||||||
#define __SEMIHOST_FS_H__
|
#define SEMIHOST_FS_H_
|
||||||
|
|
||||||
EFI_STATUS
|
EFI_STATUS
|
||||||
VolumeOpen (
|
VolumeOpen (
|
||||||
@@ -242,5 +242,5 @@ FileFlush (
|
|||||||
IN EFI_FILE *File
|
IN EFI_FILE *File
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __SEMIHOST_FS_H__
|
#endif // SEMIHOST_FS_H_
|
||||||
|
|
||||||
|
@@ -10,8 +10,8 @@
|
|||||||
**/
|
**/
|
||||||
|
|
||||||
|
|
||||||
#ifndef __MACRO_IO_LIB_H__
|
#ifndef ASM_MACRO_IO_LIB_H_
|
||||||
#define __MACRO_IO_LIB_H__
|
#define ASM_MACRO_IO_LIB_H_
|
||||||
|
|
||||||
#define _ASM_FUNC(Name, Section) \
|
#define _ASM_FUNC(Name, Section) \
|
||||||
.global Name ; \
|
.global Name ; \
|
||||||
@@ -36,4 +36,4 @@
|
|||||||
movt Reg, #:upper16:(Sym) - (. + 12) ; \
|
movt Reg, #:upper16:(Sym) - (. + 12) ; \
|
||||||
ldr Reg, [pc, Reg]
|
ldr Reg, [pc, Reg]
|
||||||
|
|
||||||
#endif
|
#endif // ASM_MACRO_IO_LIB_H_
|
||||||
|
@@ -10,8 +10,8 @@
|
|||||||
**/
|
**/
|
||||||
|
|
||||||
|
|
||||||
#ifndef __MACRO_IO_LIBV8_H__
|
#ifndef ASM_MACRO_IO_LIBV8_H_
|
||||||
#define __MACRO_IO_LIBV8_H__
|
#define ASM_MACRO_IO_LIBV8_H_
|
||||||
|
|
||||||
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
|
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
|
||||||
// This only selects between EL1 and EL2, else we die.
|
// This only selects between EL1 and EL2, else we die.
|
||||||
@@ -54,4 +54,4 @@
|
|||||||
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
|
movk Reg, ((Val) >> 16) & 0xffff, lsl #16 ; \
|
||||||
movk Reg, (Val) & 0xffff
|
movk Reg, (Val) & 0xffff
|
||||||
|
|
||||||
#endif // __MACRO_IO_LIBV8_H__
|
#endif // ASM_MACRO_IO_LIBV8_H_
|
||||||
|
@@ -1,14 +1,14 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Copyright (c) 2011 - 2017, ARM Ltd. All rights reserved.<BR>
|
Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __AARCH64_H__
|
#ifndef AARCH64_H_
|
||||||
#define __AARCH64_H__
|
#define AARCH64_H_
|
||||||
|
|
||||||
#include <Chipset/AArch64Mmu.h>
|
#include <Chipset/AArch64Mmu.h>
|
||||||
|
|
||||||
@@ -39,7 +39,7 @@
|
|||||||
// MIDR - Main ID Register definitions
|
// MIDR - Main ID Register definitions
|
||||||
#define ARM_CPU_TYPE_SHIFT 4
|
#define ARM_CPU_TYPE_SHIFT 4
|
||||||
#define ARM_CPU_TYPE_MASK 0xFFF
|
#define ARM_CPU_TYPE_MASK 0xFFF
|
||||||
#define ARM_CPU_TYPE_AEMv8 0xD0F
|
#define ARM_CPU_TYPE_AEMV8 0xD0F
|
||||||
#define ARM_CPU_TYPE_A53 0xD03
|
#define ARM_CPU_TYPE_A53 0xD03
|
||||||
#define ARM_CPU_TYPE_A57 0xD07
|
#define ARM_CPU_TYPE_A57 0xD07
|
||||||
#define ARM_CPU_TYPE_A72 0xD08
|
#define ARM_CPU_TYPE_A72 0xD08
|
||||||
@@ -97,10 +97,10 @@
|
|||||||
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
|
#define ARM_VECTOR_CUR_SP0_FIQ 0x100
|
||||||
#define ARM_VECTOR_CUR_SP0_SERR 0x180
|
#define ARM_VECTOR_CUR_SP0_SERR 0x180
|
||||||
|
|
||||||
#define ARM_VECTOR_CUR_SPx_SYNC 0x200
|
#define ARM_VECTOR_CUR_SPX_SYNC 0x200
|
||||||
#define ARM_VECTOR_CUR_SPx_IRQ 0x280
|
#define ARM_VECTOR_CUR_SPX_IRQ 0x280
|
||||||
#define ARM_VECTOR_CUR_SPx_FIQ 0x300
|
#define ARM_VECTOR_CUR_SPX_FIQ 0x300
|
||||||
#define ARM_VECTOR_CUR_SPx_SERR 0x380
|
#define ARM_VECTOR_CUR_SPX_SERR 0x380
|
||||||
|
|
||||||
#define ARM_VECTOR_LOW_A64_SYNC 0x400
|
#define ARM_VECTOR_LOW_A64_SYNC 0x400
|
||||||
#define ARM_VECTOR_LOW_A64_IRQ 0x480
|
#define ARM_VECTOR_LOW_A64_IRQ 0x480
|
||||||
@@ -112,6 +112,10 @@
|
|||||||
#define ARM_VECTOR_LOW_A32_FIQ 0x700
|
#define ARM_VECTOR_LOW_A32_FIQ 0x700
|
||||||
#define ARM_VECTOR_LOW_A32_SERR 0x780
|
#define ARM_VECTOR_LOW_A32_SERR 0x780
|
||||||
|
|
||||||
|
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
|
||||||
|
// build for ARMv8.0, we need to define the register here.
|
||||||
|
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
|
||||||
|
|
||||||
#define VECTOR_BASE(tbl) \
|
#define VECTOR_BASE(tbl) \
|
||||||
.section .text.##tbl##,"ax"; \
|
.section .text.##tbl##,"ax"; \
|
||||||
.align 11; \
|
.align 11; \
|
||||||
@@ -234,4 +238,4 @@ ArmWriteCntHctl (
|
|||||||
IN UINT32 CntHctl
|
IN UINT32 CntHctl
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __AARCH64_H__
|
#endif // AARCH64_H_
|
||||||
|
@@ -1,13 +1,13 @@
|
|||||||
/** @file
|
/** @file
|
||||||
*
|
*
|
||||||
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __AARCH64_MMU_H_
|
#ifndef AARCH64_MMU_H_
|
||||||
#define __AARCH64_MMU_H_
|
#define AARCH64_MMU_H_
|
||||||
|
|
||||||
//
|
//
|
||||||
// Memory Attribute Indirection register Definitions
|
// Memory Attribute Indirection register Definitions
|
||||||
@@ -190,9 +190,9 @@
|
|||||||
|
|
||||||
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
|
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
|
||||||
// Virtual address range for 512GB of virtual space sets T*SZ to 25
|
// Virtual address range for 512GB of virtual space sets T*SZ to 25
|
||||||
#define INPUT_ADDRESS_SIZE_TO_TxSZ(a) (64 - a)
|
#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
|
||||||
|
|
||||||
// Uses LPAE Page Table format
|
// Uses LPAE Page Table format
|
||||||
|
|
||||||
#endif // __AARCH64_MMU_H_
|
#endif // AARCH64_MMU_H_
|
||||||
|
|
||||||
|
@@ -1,13 +1,13 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2012-2014, ARM Limited. All rights reserved.
|
Copyright (c) 2012 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_CORTEX_A5x_H__
|
#ifndef ARM_CORTEX_A5X_H_
|
||||||
#define __ARM_CORTEX_A5x_H__
|
#define ARM_CORTEX_A5X_H_
|
||||||
|
|
||||||
//
|
//
|
||||||
// Cortex A5x feature bit definitions
|
// Cortex A5x feature bit definitions
|
||||||
@@ -41,4 +41,4 @@ ArmUnsetCpuExCrBit (
|
|||||||
IN UINT64 Bits
|
IN UINT64 Bits
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_CORTEX_A5X_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_CORTEX_A9_H__
|
#ifndef ARM_CORTEX_A9_H_
|
||||||
#define __ARM_CORTEX_A9_H__
|
#define ARM_CORTEX_A9_H_
|
||||||
|
|
||||||
#include <Chipset/ArmV7.h>
|
#include <Chipset/ArmV7.h>
|
||||||
|
|
||||||
@@ -55,5 +55,5 @@ ArmGetScuBaseAddress (
|
|||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_CORTEX_A9_H_
|
||||||
|
|
||||||
|
@@ -1,14 +1,14 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>
|
Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_V7_H__
|
#ifndef ARM_V7_H_
|
||||||
#define __ARM_V7_H__
|
#define ARM_V7_H_
|
||||||
|
|
||||||
#include <Chipset/ArmV7Mmu.h>
|
#include <Chipset/ArmV7Mmu.h>
|
||||||
|
|
||||||
@@ -70,7 +70,7 @@
|
|||||||
// MIDR - Main ID Register definitions
|
// MIDR - Main ID Register definitions
|
||||||
#define ARM_CPU_TYPE_SHIFT 4
|
#define ARM_CPU_TYPE_SHIFT 4
|
||||||
#define ARM_CPU_TYPE_MASK 0xFFF
|
#define ARM_CPU_TYPE_MASK 0xFFF
|
||||||
#define ARM_CPU_TYPE_AEMv8 0xD0F
|
#define ARM_CPU_TYPE_AEMV8 0xD0F
|
||||||
#define ARM_CPU_TYPE_A53 0xD03
|
#define ARM_CPU_TYPE_A53 0xD03
|
||||||
#define ARM_CPU_TYPE_A57 0xD07
|
#define ARM_CPU_TYPE_A57 0xD07
|
||||||
#define ARM_CPU_TYPE_A15 0xC0F
|
#define ARM_CPU_TYPE_A15 0xC0F
|
||||||
@@ -120,4 +120,4 @@ ArmWriteNsacr (
|
|||||||
IN UINT32 Nsacr
|
IN UINT32 Nsacr
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __ARM_V7_H__
|
#endif // ARM_V7_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARMV7_MMU_H_
|
#ifndef ARMV7_MMU_H_
|
||||||
#define __ARMV7_MMU_H_
|
#define ARMV7_MMU_H_
|
||||||
|
|
||||||
#define TTBR_NOT_OUTER_SHAREABLE BIT5
|
#define TTBR_NOT_OUTER_SHAREABLE BIT5
|
||||||
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
|
#define TTBR_RGN_OUTER_NON_CACHEABLE 0
|
||||||
@@ -235,4 +235,4 @@ ConvertSectionAttributesToPageAttributes (
|
|||||||
IN BOOLEAN IsLargePage
|
IN BOOLEAN IsLargePage
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARMV7_MMU_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_MP_CORE_INFO_GUID_H_
|
#ifndef ARM_MP_CORE_INFO_GUID_H_
|
||||||
#define __ARM_MP_CORE_INFO_GUID_H_
|
#define ARM_MP_CORE_INFO_GUID_H_
|
||||||
|
|
||||||
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
|
#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
|
||||||
#define SCU_CONFIG_REG_OFFSET 0x04
|
#define SCU_CONFIG_REG_OFFSET 0x04
|
||||||
@@ -57,4 +57,4 @@ typedef struct {
|
|||||||
|
|
||||||
extern EFI_GUID gArmMpCoreInfoGuid;
|
extern EFI_GUID gArmMpCoreInfoGuid;
|
||||||
|
|
||||||
#endif /* MPCOREINFO_H_ */
|
#endif /* ARM_MP_CORE_INFO_GUID_H_ */
|
||||||
|
112
ArmPkg/Include/IndustryStandard/ArmCache.h
Normal file
112
ArmPkg/Include/IndustryStandard/ArmCache.h
Normal file
@@ -0,0 +1,112 @@
|
|||||||
|
/** @file
|
||||||
|
|
||||||
|
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
|
||||||
|
|
||||||
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef ARM_CACHE_H_
|
||||||
|
#define ARM_CACHE_H_
|
||||||
|
|
||||||
|
#include <Uefi/UefiBaseType.h>
|
||||||
|
|
||||||
|
// The ARM Architecture Reference Manual for ARMv8-A defines up
|
||||||
|
// to 7 levels of cache, L1 through L7.
|
||||||
|
#define MAX_ARM_CACHE_LEVEL 7
|
||||||
|
|
||||||
|
/// Defines the structure of the CSSELR (Cache Size Selection) register
|
||||||
|
typedef union {
|
||||||
|
struct {
|
||||||
|
UINT32 InD :1; ///< Instruction not Data bit
|
||||||
|
UINT32 Level :3; ///< Cache level (zero based)
|
||||||
|
UINT32 TnD :1; ///< Allocation not Data bit
|
||||||
|
UINT32 Reserved :27; ///< Reserved, RES0
|
||||||
|
} Bits; ///< Bitfield definition of the register
|
||||||
|
UINT32 Data; ///< The entire 32-bit value
|
||||||
|
} CSSELR_DATA;
|
||||||
|
|
||||||
|
/// The cache type values for the InD field of the CSSELR register
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
/// Select the data or unified cache
|
||||||
|
CsselrCacheTypeDataOrUnified = 0,
|
||||||
|
/// Select the instruction cache
|
||||||
|
CsselrCacheTypeInstruction,
|
||||||
|
CsselrCacheTypeMax
|
||||||
|
} CSSELR_CACHE_TYPE;
|
||||||
|
|
||||||
|
/// Defines the structure of the CCSIDR (Current Cache Size ID) register
|
||||||
|
typedef union {
|
||||||
|
struct {
|
||||||
|
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
|
||||||
|
UINT64 Associativity :10; ///< Associativity - 1
|
||||||
|
UINT64 NumSets :15; ///< Number of sets in the cache -1
|
||||||
|
UINT64 Unknown :4; ///< Reserved, UNKNOWN
|
||||||
|
UINT64 Reserved :32; ///< Reserved, RES0
|
||||||
|
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
|
||||||
|
struct {
|
||||||
|
UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
|
||||||
|
UINT64 Associativity :21; ///< Associativity - 1
|
||||||
|
UINT64 Reserved1 :8; ///< Reserved, RES0
|
||||||
|
UINT64 NumSets :24; ///< Number of sets in the cache -1
|
||||||
|
UINT64 Reserved2 :8; ///< Reserved, RES0
|
||||||
|
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
|
||||||
|
struct {
|
||||||
|
UINT64 LineSize : 3;
|
||||||
|
UINT64 Associativity : 21;
|
||||||
|
UINT64 Reserved : 8;
|
||||||
|
UINT64 Unallocated : 32;
|
||||||
|
} BitsCcidxAA32;
|
||||||
|
UINT64 Data; ///< The entire 64-bit value
|
||||||
|
} CCSIDR_DATA;
|
||||||
|
|
||||||
|
/// Defines the structure of the AARCH32 CCSIDR2 register.
|
||||||
|
typedef union {
|
||||||
|
struct {
|
||||||
|
UINT32 NumSets :24; ///< Number of sets in the cache - 1
|
||||||
|
UINT32 Reserved :8; ///< Reserved, RES0
|
||||||
|
} Bits; ///< Bitfield definition of the register
|
||||||
|
UINT32 Data; ///< The entire 32-bit value
|
||||||
|
} CCSIDR2_DATA;
|
||||||
|
|
||||||
|
/** Defines the structure of the CLIDR (Cache Level ID) register.
|
||||||
|
*
|
||||||
|
* The lower 32 bits are the same for both AARCH32 and AARCH64
|
||||||
|
* so we can use the same structure for both.
|
||||||
|
**/
|
||||||
|
typedef union {
|
||||||
|
struct {
|
||||||
|
UINT32 Ctype1 : 3; ///< Level 1 cache type
|
||||||
|
UINT32 Ctype2 : 3; ///< Level 2 cache type
|
||||||
|
UINT32 Ctype3 : 3; ///< Level 3 cache type
|
||||||
|
UINT32 Ctype4 : 3; ///< Level 4 cache type
|
||||||
|
UINT32 Ctype5 : 3; ///< Level 5 cache type
|
||||||
|
UINT32 Ctype6 : 3; ///< Level 6 cache type
|
||||||
|
UINT32 Ctype7 : 3; ///< Level 7 cache type
|
||||||
|
UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
|
||||||
|
UINT32 LoC : 3; ///< Level of Coherency
|
||||||
|
UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
|
||||||
|
UINT32 Icb : 3; ///< Inner Cache Boundary
|
||||||
|
} Bits; ///< Bitfield definition of the register
|
||||||
|
UINT32 Data; ///< The entire 32-bit value
|
||||||
|
} CLIDR_DATA;
|
||||||
|
|
||||||
|
/// The cache types reported in the CLIDR register.
|
||||||
|
typedef enum {
|
||||||
|
/// No cache is present
|
||||||
|
ClidrCacheTypeNone = 0,
|
||||||
|
/// There is only an instruction cache
|
||||||
|
ClidrCacheTypeInstructionOnly,
|
||||||
|
/// There is only a data cache
|
||||||
|
ClidrCacheTypeDataOnly,
|
||||||
|
/// There are separate data and instruction caches
|
||||||
|
ClidrCacheTypeSeparate,
|
||||||
|
/// There is a unified cache
|
||||||
|
ClidrCacheTypeUnified,
|
||||||
|
ClidrCacheTypeMax
|
||||||
|
} CLIDR_CACHE_TYPE;
|
||||||
|
|
||||||
|
#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
|
||||||
|
|
||||||
|
#endif /* ARM_CACHE_H_ */
|
44
ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
Normal file
44
ArmPkg/Include/IndustryStandard/ArmFfaSvc.h
Normal file
@@ -0,0 +1,44 @@
|
|||||||
|
/** @file
|
||||||
|
Header file for FF-A ABI's that will be used for
|
||||||
|
communication between S-EL0 and the Secure Partition
|
||||||
|
Manager(SPM)
|
||||||
|
|
||||||
|
Copyright (c) 2020, ARM Limited. All rights reserved.
|
||||||
|
|
||||||
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
|
@par Revision Reference:
|
||||||
|
- FF-A Version 1.0
|
||||||
|
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#ifndef ARM_FFA_SVC_H_
|
||||||
|
#define ARM_FFA_SVC_H_
|
||||||
|
|
||||||
|
#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
|
||||||
|
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
|
||||||
|
#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
|
||||||
|
|
||||||
|
#define SPM_MAJOR_VERSION_FFA 1
|
||||||
|
#define SPM_MINOR_VERSION_FFA 0
|
||||||
|
|
||||||
|
#define ARM_FFA_SPM_RET_SUCCESS 0
|
||||||
|
#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
|
||||||
|
#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
|
||||||
|
#define ARM_FFA_SPM_RET_NO_MEMORY -3
|
||||||
|
#define ARM_FFA_SPM_RET_BUSY -4
|
||||||
|
#define ARM_FFA_SPM_RET_INTERRUPTED -5
|
||||||
|
#define ARM_FFA_SPM_RET_DENIED -6
|
||||||
|
#define ARM_FFA_SPM_RET_RETRY -7
|
||||||
|
#define ARM_FFA_SPM_RET_ABORTED -8
|
||||||
|
|
||||||
|
// For now, the destination id to be used in the FF-A calls
|
||||||
|
// is being hard-coded. Subsequently, support will be added
|
||||||
|
// to get the endpoint id's dynamically
|
||||||
|
// This is the endpoint id used by the optee os's implementation
|
||||||
|
// of the spmc.
|
||||||
|
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
|
||||||
|
#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
|
||||||
|
|
||||||
|
#endif // ARM_FFA_SVC_H_
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_MM_SVC_H__
|
#ifndef ARM_MM_SVC_H_
|
||||||
#define __ARM_MM_SVC_H__
|
#define ARM_MM_SVC_H_
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SVC IDs to allow the MM secure partition to initialise itself, handle
|
* SVC IDs to allow the MM secure partition to initialise itself, handle
|
||||||
@@ -41,4 +41,7 @@
|
|||||||
#define ARM_SVC_SPM_RET_DENIED -3
|
#define ARM_SVC_SPM_RET_DENIED -3
|
||||||
#define ARM_SVC_SPM_RET_NO_MEMORY -5
|
#define ARM_SVC_SPM_RET_NO_MEMORY -5
|
||||||
|
|
||||||
#endif
|
#define SPM_MAJOR_VERSION 0
|
||||||
|
#define SPM_MINOR_VERSION 1
|
||||||
|
|
||||||
|
#endif // ARM_MM_SVC_H_
|
||||||
|
@@ -1,13 +1,17 @@
|
|||||||
/** @file
|
/** @file
|
||||||
*
|
*
|
||||||
|
* Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
|
||||||
* Copyright (c) 2012-2017, ARM Limited. All rights reserved.
|
* Copyright (c) 2012-2017, ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
|
* @par Revision Reference:
|
||||||
|
* - SMC Calling Convention version 1.2
|
||||||
|
* (https://developer.arm.com/documentation/den0028/c/?lang=en)
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_STD_SMC_H__
|
#ifndef ARM_STD_SMC_H_
|
||||||
#define __ARM_STD_SMC_H__
|
#define ARM_STD_SMC_H_
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SMC function IDs for Standard Service queries
|
* SMC function IDs for Standard Service queries
|
||||||
@@ -52,6 +56,18 @@
|
|||||||
#define ARM_SMC_MM_RET_DENIED -3
|
#define ARM_SMC_MM_RET_DENIED -3
|
||||||
#define ARM_SMC_MM_RET_NO_MEMORY -4
|
#define ARM_SMC_MM_RET_NO_MEMORY -4
|
||||||
|
|
||||||
|
// ARM Architecture Calls
|
||||||
|
#define SMCCC_VERSION 0x80000000
|
||||||
|
#define SMCCC_ARCH_FEATURES 0x80000001
|
||||||
|
#define SMCCC_ARCH_SOC_ID 0x80000002
|
||||||
|
#define SMCCC_ARCH_WORKAROUND_1 0x80008000
|
||||||
|
#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
|
||||||
|
|
||||||
|
#define SMC_ARCH_CALL_SUCCESS 0
|
||||||
|
#define SMC_ARCH_CALL_NOT_SUPPORTED -1
|
||||||
|
#define SMC_ARCH_CALL_NOT_REQUIRED -2
|
||||||
|
#define SMC_ARCH_CALL_INVALID_PARAMETER -3
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Power State Coordination Interface (PSCI) calls cover a subset of the
|
* Power State Coordination Interface (PSCI) calls cover a subset of the
|
||||||
* Standard Service Call range.
|
* Standard Service Call range.
|
||||||
@@ -113,4 +129,4 @@
|
|||||||
/* 0xbf00ff02 is reserved */
|
/* 0xbf00ff02 is reserved */
|
||||||
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
|
#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
|
||||||
|
|
||||||
#endif
|
#endif // ARM_STD_SMC_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_DISASSEBLER_LIB_H__
|
#ifndef ARM_DISASSEMBLER_LIB_H_
|
||||||
#define __ARM_DISASSEBLER_LIB_H__
|
#define ARM_DISASSEMBLER_LIB_H_
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
|
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
|
||||||
@@ -34,4 +34,4 @@ DisassembleInstruction (
|
|||||||
OUT UINTN Size
|
OUT UINTN Size
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_DISASSEMBLER_LIB_H_
|
||||||
|
@@ -7,8 +7,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_GENERIC_TIMER_COUNTER_LIB_H__
|
#ifndef ARM_GENERIC_TIMER_COUNTER_LIB_H_
|
||||||
#define __ARM_GENERIC_TIMER_COUNTER_LIB_H__
|
#define ARM_GENERIC_TIMER_COUNTER_LIB_H_
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
@@ -82,4 +82,4 @@ ArmGenericTimerSetCompareVal (
|
|||||||
IN UINT64 Value
|
IN UINT64 Value
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_GIC_ARCH_LIB_H__
|
#ifndef ARM_GIC_ARCH_LIB_H_
|
||||||
#define __ARM_GIC_ARCH_LIB_H__
|
#define ARM_GIC_ARCH_LIB_H_
|
||||||
|
|
||||||
//
|
//
|
||||||
// GIC definitions
|
// GIC definitions
|
||||||
@@ -24,4 +24,4 @@ ArmGicGetSupportedArchRevision (
|
|||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_GIC_ARCH_LIB_H_
|
||||||
|
@@ -1,13 +1,13 @@
|
|||||||
/** @file
|
/** @file
|
||||||
*
|
*
|
||||||
* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
|
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARMGIC_H
|
#ifndef ARMGIC_H_
|
||||||
#define __ARMGIC_H
|
#define ARMGIC_H_
|
||||||
|
|
||||||
#include <Library/ArmGicArchLib.h>
|
#include <Library/ArmGicArchLib.h>
|
||||||
|
|
||||||
@@ -208,6 +208,15 @@ ArmGicSetPriorityMask (
|
|||||||
IN INTN PriorityMask
|
IN INTN PriorityMask
|
||||||
);
|
);
|
||||||
|
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
ArmGicSetInterruptPriority (
|
||||||
|
IN UINTN GicDistributorBase,
|
||||||
|
IN UINTN GicRedistributorBase,
|
||||||
|
IN UINTN Source,
|
||||||
|
IN UINTN Priority
|
||||||
|
);
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmGicEnableInterrupt (
|
ArmGicEnableInterrupt (
|
||||||
@@ -324,4 +333,4 @@ ArmGicV3SetPriorityMask (
|
|||||||
IN UINTN Priority
|
IN UINTN Priority
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARMGIC_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_HVC_LIB__
|
#ifndef ARM_HVC_LIB_H_
|
||||||
#define __ARM_HVC_LIB__
|
#define ARM_HVC_LIB_H_
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* The size of the HVC arguments are different between AArch64 and AArch32.
|
* The size of the HVC arguments are different between AArch64 and AArch32.
|
||||||
@@ -37,4 +37,4 @@ ArmCallHvc (
|
|||||||
IN OUT ARM_HVC_ARGS *Args
|
IN OUT ARM_HVC_ARGS *Args
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_HVC_LIB_H_
|
||||||
|
@@ -2,13 +2,14 @@
|
|||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
|
Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_LIB__
|
#ifndef ARM_LIB_H_
|
||||||
#define __ARM_LIB__
|
#define ARM_LIB_H_
|
||||||
|
|
||||||
#include <Uefi/UefiBaseType.h>
|
#include <Uefi/UefiBaseType.h>
|
||||||
|
|
||||||
@@ -108,6 +109,38 @@ typedef enum {
|
|||||||
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
|
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
|
||||||
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
|
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
|
||||||
|
|
||||||
|
/** Reads the CCSIDR register for the specified cache.
|
||||||
|
|
||||||
|
@param CSSELR The CSSELR cache selection register value.
|
||||||
|
|
||||||
|
@return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.
|
||||||
|
Returns the contents of the CCSIDR register in AARCH32 mode.
|
||||||
|
**/
|
||||||
|
UINTN
|
||||||
|
ReadCCSIDR (
|
||||||
|
IN UINT32 CSSELR
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Reads the CCSIDR2 for the specified cache.
|
||||||
|
|
||||||
|
@param CSSELR The CSSELR cache selection register value
|
||||||
|
|
||||||
|
@return The contents of the CCSIDR2 register for the specified cache.
|
||||||
|
**/
|
||||||
|
UINT32
|
||||||
|
ReadCCSIDR2 (
|
||||||
|
IN UINT32 CSSELR
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Reads the Cache Level ID (CLIDR) register.
|
||||||
|
|
||||||
|
@return The contents of the CLIDR_EL1 register.
|
||||||
|
**/
|
||||||
|
UINT32
|
||||||
|
ReadCLIDR (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
UINTN
|
UINTN
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmDataCacheLineLength (
|
ArmDataCacheLineLength (
|
||||||
@@ -132,18 +165,6 @@ ArmIsArchTimerImplemented (
|
|||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
UINTN
|
|
||||||
EFIAPI
|
|
||||||
ArmReadIdPfr0 (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
UINTN
|
|
||||||
EFIAPI
|
|
||||||
ArmReadIdPfr1 (
|
|
||||||
VOID
|
|
||||||
);
|
|
||||||
|
|
||||||
UINTN
|
UINTN
|
||||||
EFIAPI
|
EFIAPI
|
||||||
ArmCacheInfo (
|
ArmCacheInfo (
|
||||||
@@ -715,4 +736,49 @@ ArmGetPhysicalAddressBits (
|
|||||||
VOID
|
VOID
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __ARM_LIB__
|
|
||||||
|
///
|
||||||
|
/// ID Register Helper functions
|
||||||
|
///
|
||||||
|
|
||||||
|
/**
|
||||||
|
Check whether the CPU supports the GIC system register interface (any version)
|
||||||
|
|
||||||
|
@return Whether GIC System Register Interface is supported
|
||||||
|
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
ArmHasGicSystemRegisters (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Checks if CCIDX is implemented.
|
||||||
|
|
||||||
|
@retval TRUE CCIDX is implemented.
|
||||||
|
@retval FALSE CCIDX is not implemented.
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
ArmHasCcidx (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
#ifdef MDE_CPU_ARM
|
||||||
|
///
|
||||||
|
/// AArch32-only ID Register Helper functions
|
||||||
|
///
|
||||||
|
/**
|
||||||
|
Check whether the CPU supports the Security extensions
|
||||||
|
|
||||||
|
@return Whether the Security extensions are implemented
|
||||||
|
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
ArmHasSecurityExtensions (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
#endif // MDE_CPU_ARM
|
||||||
|
|
||||||
|
#endif // ARM_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_MMU_LIB__
|
#ifndef ARM_MMU_LIB_H_
|
||||||
#define __ARM_MMU_LIB__
|
#define ARM_MMU_LIB_H_
|
||||||
|
|
||||||
#include <Uefi/UefiBaseType.h>
|
#include <Uefi/UefiBaseType.h>
|
||||||
|
|
||||||
@@ -64,4 +64,4 @@ ArmSetMemoryAttributes (
|
|||||||
IN UINT64 Attributes
|
IN UINT64 Attributes
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_MMU_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_SMC_LIB__
|
#ifndef ARM_SMC_LIB_H_
|
||||||
#define __ARM_SMC_LIB__
|
#define ARM_SMC_LIB_H_
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* The size of the SMC arguments are different between AArch64 and AArch32.
|
* The size of the SMC arguments are different between AArch64 and AArch32.
|
||||||
@@ -37,4 +37,4 @@ ArmCallSmc (
|
|||||||
IN OUT ARM_SMC_ARGS *Args
|
IN OUT ARM_SMC_ARGS *Args
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_SMC_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_SVC_LIB__
|
#ifndef ARM_SVC_LIB_H_
|
||||||
#define __ARM_SVC_LIB__
|
#define ARM_SVC_LIB_H_
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* The size of the SVC arguments are different between AArch64 and AArch32.
|
* The size of the SVC arguments are different between AArch64 and AArch32.
|
||||||
@@ -27,14 +27,20 @@ typedef struct {
|
|||||||
/**
|
/**
|
||||||
Trigger an SVC call
|
Trigger an SVC call
|
||||||
|
|
||||||
SVC calls can take up to 7 arguments and return up to 4 return values.
|
SVC calls can take up to 8 arguments and return up to 8 return values.
|
||||||
Therefore, the 4 first fields in the ARM_SVC_ARGS structure are used
|
Therefore, the 8 first fields in the ARM_SVC_ARGS structure are used
|
||||||
for both input and output values.
|
for both input and output values.
|
||||||
|
|
||||||
|
@param[in, out] Args Arguments to be passed as part of the SVC call
|
||||||
|
The return values of the SVC call are also placed
|
||||||
|
in the same structure
|
||||||
|
|
||||||
|
@retval None
|
||||||
|
|
||||||
**/
|
**/
|
||||||
VOID
|
VOID
|
||||||
ArmCallSvc (
|
ArmCallSvc (
|
||||||
IN OUT ARM_SVC_ARGS *Args
|
IN OUT ARM_SVC_ARGS *Args
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // ARM_SVC_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __DEFAULT_EXCEPTION_HANDLER_LIB_H__
|
#ifndef DEFAULT_EXCEPTION_HANDLER_LIB_H_
|
||||||
#define __DEFAULT_EXCEPTION_HANDLER_LIB_H__
|
#define DEFAULT_EXCEPTION_HANDLER_LIB_H_
|
||||||
|
|
||||||
/**
|
/**
|
||||||
This is the default action to take on an unexpected exception
|
This is the default action to take on an unexpected exception
|
||||||
@@ -22,4 +22,4 @@ DefaultExceptionHandler (
|
|||||||
IN OUT EFI_SYSTEM_CONTEXT SystemContext
|
IN OUT EFI_SYSTEM_CONTEXT SystemContext
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_
|
||||||
|
235
ArmPkg/Include/Library/OemMiscLib.h
Normal file
235
ArmPkg/Include/Library/OemMiscLib.h
Normal file
@@ -0,0 +1,235 @@
|
|||||||
|
/** @file
|
||||||
|
*
|
||||||
|
* Copyright (c) 2021, NUVIA Inc. All rights reserved.
|
||||||
|
* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2015, Linaro Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
*
|
||||||
|
**/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef OEM_MISC_LIB_H_
|
||||||
|
#define OEM_MISC_LIB_H_
|
||||||
|
|
||||||
|
#include <Uefi.h>
|
||||||
|
#include <IndustryStandard/SmBios.h>
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CpuCacheL1 = 1,
|
||||||
|
CpuCacheL2,
|
||||||
|
CpuCacheL3,
|
||||||
|
CpuCacheL4,
|
||||||
|
CpuCacheL5,
|
||||||
|
CpuCacheL6,
|
||||||
|
CpuCacheL7,
|
||||||
|
CpuCacheLevelMax
|
||||||
|
} OEM_MISC_CPU_CACHE_LEVEL;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
UINT8 Voltage; ///< Processor voltage
|
||||||
|
UINT16 CurrentSpeed; ///< Current clock speed in MHz
|
||||||
|
UINT16 MaxSpeed; ///< Maximum clock speed in MHz
|
||||||
|
UINT16 ExternalClock; ///< External clock speed in MHz
|
||||||
|
UINT16 CoreCount; ///< Number of cores available
|
||||||
|
UINT16 CoresEnabled; ///< Number of cores enabled
|
||||||
|
UINT16 ThreadCount; ///< Number of threads per processor
|
||||||
|
} OEM_MISC_PROCESSOR_DATA;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
ProductNameType01,
|
||||||
|
SerialNumType01,
|
||||||
|
UuidType01,
|
||||||
|
SystemManufacturerType01,
|
||||||
|
SkuNumberType01,
|
||||||
|
FamilyType01,
|
||||||
|
AssertTagType02,
|
||||||
|
SerialNumberType02,
|
||||||
|
BoardManufacturerType02,
|
||||||
|
SkuNumberType02,
|
||||||
|
ChassisLocationType02,
|
||||||
|
AssetTagType03,
|
||||||
|
SerialNumberType03,
|
||||||
|
VersionType03,
|
||||||
|
ChassisTypeType03,
|
||||||
|
ManufacturerType03,
|
||||||
|
SkuNumberType03,
|
||||||
|
SmbiosHiiStringFieldMax
|
||||||
|
} OEM_MISC_SMBIOS_HII_STRING_FIELD;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The following are functions that the each platform needs to
|
||||||
|
* implement in its OemMiscLib library.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** Gets the CPU frequency of the specified processor.
|
||||||
|
|
||||||
|
@param ProcessorIndex Index of the processor to get the frequency for.
|
||||||
|
|
||||||
|
@return CPU frequency in Hz
|
||||||
|
**/
|
||||||
|
UINTN
|
||||||
|
EFIAPI
|
||||||
|
OemGetCpuFreq (
|
||||||
|
IN UINT8 ProcessorIndex
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Gets information about the specified processor and stores it in
|
||||||
|
the structures provided.
|
||||||
|
|
||||||
|
@param ProcessorIndex Index of the processor to get the information for.
|
||||||
|
@param ProcessorStatus Processor status.
|
||||||
|
@param ProcessorCharacteristics Processor characteritics.
|
||||||
|
@param MiscProcessorData Miscellaneous processor information.
|
||||||
|
|
||||||
|
@return TRUE on success, FALSE on failure.
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
OemGetProcessorInformation (
|
||||||
|
IN UINTN ProcessorIndex,
|
||||||
|
IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
|
||||||
|
IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
|
||||||
|
IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Gets information about the cache at the specified cache level.
|
||||||
|
|
||||||
|
@param ProcessorIndex The processor to get information for.
|
||||||
|
@param CacheLevel The cache level to get information for.
|
||||||
|
@param DataCache Whether the cache is a data cache.
|
||||||
|
@param UnifiedCache Whether the cache is a unified cache.
|
||||||
|
@param SmbiosCacheTable The SMBIOS Type7 cache information structure.
|
||||||
|
|
||||||
|
@return TRUE on success, FALSE on failure.
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
OemGetCacheInformation (
|
||||||
|
IN UINT8 ProcessorIndex,
|
||||||
|
IN UINT8 CacheLevel,
|
||||||
|
IN BOOLEAN DataCache,
|
||||||
|
IN BOOLEAN UnifiedCache,
|
||||||
|
IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Gets the maximum number of processors supported by the platform.
|
||||||
|
|
||||||
|
@return The maximum number of processors.
|
||||||
|
**/
|
||||||
|
UINT8
|
||||||
|
EFIAPI
|
||||||
|
OemGetMaxProcessors (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Gets the type of chassis for the system.
|
||||||
|
|
||||||
|
@retval The type of the chassis.
|
||||||
|
**/
|
||||||
|
MISC_CHASSIS_TYPE
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisType (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Returns whether the specified processor is present or not.
|
||||||
|
|
||||||
|
@param ProcessIndex The processor index to check.
|
||||||
|
|
||||||
|
@return TRUE is the processor is present, FALSE otherwise.
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
OemIsProcessorPresent (
|
||||||
|
IN UINTN ProcessorIndex
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Updates the HII string for the specified field.
|
||||||
|
|
||||||
|
@param HiiHandle The HII handle.
|
||||||
|
@param TokenToUpdate The string to update.
|
||||||
|
@param Field The field to get information about.
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
OemUpdateSmbiosInfo (
|
||||||
|
IN EFI_HII_HANDLE HiiHandle,
|
||||||
|
IN EFI_STRING_ID TokenToUpdate,
|
||||||
|
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the Type 32 boot information status.
|
||||||
|
|
||||||
|
@return Boot status.
|
||||||
|
**/
|
||||||
|
MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
|
||||||
|
EFIAPI
|
||||||
|
OemGetBootStatus (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the chassis status when it was last booted.
|
||||||
|
|
||||||
|
@return Chassis status.
|
||||||
|
**/
|
||||||
|
MISC_CHASSIS_STATE
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisBootupState (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the chassis power supply/supplies status when last booted.
|
||||||
|
|
||||||
|
@return Chassis power supply/supplies status.
|
||||||
|
**/
|
||||||
|
MISC_CHASSIS_STATE
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisPowerSupplyState (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the chassis thermal status when last booted.
|
||||||
|
|
||||||
|
@return Chassis thermal status.
|
||||||
|
**/
|
||||||
|
MISC_CHASSIS_STATE
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisThermalState (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the chassis security status when last booted.
|
||||||
|
|
||||||
|
@return Chassis security status.
|
||||||
|
**/
|
||||||
|
MISC_CHASSIS_SECURITY_STATE
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisSecurityStatus (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the chassis height in RMUs (Rack Mount Units).
|
||||||
|
|
||||||
|
@return The height of the chassis.
|
||||||
|
**/
|
||||||
|
UINT8
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisHeight (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Fetches the number of power cords.
|
||||||
|
|
||||||
|
@return The number of power cords.
|
||||||
|
**/
|
||||||
|
UINT8
|
||||||
|
EFIAPI
|
||||||
|
OemGetChassisNumPowerCords (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
#endif // OEM_MISC_LIB_H_
|
@@ -2,13 +2,14 @@
|
|||||||
OP-TEE specific header file.
|
OP-TEE specific header file.
|
||||||
|
|
||||||
Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
|
Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef _OPTEE_H_
|
#ifndef OPTEE_LIB_H_
|
||||||
#define _OPTEE_H_
|
#define OPTEE_LIB_H_
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The 'Trusted OS Call UID' is supposed to return the following UUID for
|
* The 'Trusted OS Call UID' is supposed to return the following UUID for
|
||||||
@@ -45,12 +46,14 @@ typedef struct {
|
|||||||
UINT64 C;
|
UINT64 C;
|
||||||
} OPTEE_MESSAGE_PARAM_VALUE;
|
} OPTEE_MESSAGE_PARAM_VALUE;
|
||||||
|
|
||||||
typedef struct {
|
typedef union {
|
||||||
UINT64 Attribute;
|
|
||||||
union {
|
|
||||||
OPTEE_MESSAGE_PARAM_MEMORY Memory;
|
OPTEE_MESSAGE_PARAM_MEMORY Memory;
|
||||||
OPTEE_MESSAGE_PARAM_VALUE Value;
|
OPTEE_MESSAGE_PARAM_VALUE Value;
|
||||||
} Union;
|
} OPTEE_MESSAGE_PARAM_UNION;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT64 Attribute;
|
||||||
|
OPTEE_MESSAGE_PARAM_UNION Union;
|
||||||
} OPTEE_MESSAGE_PARAM;
|
} OPTEE_MESSAGE_PARAM;
|
||||||
|
|
||||||
#define OPTEE_MAX_CALL_PARAMS 4
|
#define OPTEE_MAX_CALL_PARAMS 4
|
||||||
@@ -114,4 +117,4 @@ OpteeInvokeFunction (
|
|||||||
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
|
IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif
|
#endif // OPTEE_LIB_H_
|
||||||
|
@@ -7,8 +7,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __SEMIHOSTING_H__
|
#ifndef SEMIHOSTING_LIB_H_
|
||||||
#define __SEMIHOSTING_H__
|
#define SEMIHOSTING_LIB_H_
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*
|
*
|
||||||
@@ -129,4 +129,4 @@ SemihostSystem (
|
|||||||
IN CHAR8 *CommandLine
|
IN CHAR8 *CommandLine
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __SEMIHOSTING_H__
|
#endif // SEMIHOSTING_LIB_H_
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __STANDALONEMM_MMU_LIB__
|
#ifndef STANDALONE_MM_MMU_LIB_
|
||||||
#define __STANDALONEMM_MMU_LIB__
|
#define STANDALONE_MM_MMU_LIB_
|
||||||
|
|
||||||
EFI_STATUS
|
EFI_STATUS
|
||||||
ArmSetMemoryRegionNoExec (
|
ArmSetMemoryRegionNoExec (
|
||||||
@@ -33,4 +33,4 @@ ArmClearMemoryRegionReadOnly (
|
|||||||
IN UINT64 Length
|
IN UINT64 Length
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif /* __STANDALONEMM_MMU_LIB__ */
|
#endif /* STANDALONE_MM_MMU_LIB_ */
|
||||||
|
@@ -6,8 +6,8 @@
|
|||||||
*
|
*
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __ARM_MP_CORE_INFO_PPI_H__
|
#ifndef ARM_MP_CORE_INFO_PPI_H_
|
||||||
#define __ARM_MP_CORE_INFO_PPI_H__
|
#define ARM_MP_CORE_INFO_PPI_H_
|
||||||
|
|
||||||
#include <Guid/ArmMpCoreInfo.h>
|
#include <Guid/ArmMpCoreInfo.h>
|
||||||
|
|
||||||
@@ -49,4 +49,4 @@ typedef struct {
|
|||||||
extern EFI_GUID gArmMpCoreInfoPpiGuid;
|
extern EFI_GUID gArmMpCoreInfoPpiGuid;
|
||||||
extern EFI_GUID gArmMpCoreInfoGuid;
|
extern EFI_GUID gArmMpCoreInfoGuid;
|
||||||
|
|
||||||
#endif
|
#endif // ARM_MP_CORE_INFO_PPI_H_
|
||||||
|
@@ -1,12 +1,12 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
System Control and Management Interface V1.0
|
@par Specification Reference:
|
||||||
http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
|
- Arm System Control and Management Interface - Platform Design Document
|
||||||
DEN0056A_System_Control_and_Management_Interface.pdf
|
(https://developer.arm.com/documentation/den0056/)
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef ARM_SCMI_BASE_PROTOCOL_H_
|
#ifndef ARM_SCMI_BASE_PROTOCOL_H_
|
||||||
@@ -14,7 +14,8 @@
|
|||||||
|
|
||||||
#include <Protocol/ArmScmi.h>
|
#include <Protocol/ArmScmi.h>
|
||||||
|
|
||||||
#define BASE_PROTOCOL_VERSION 0x10000
|
#define BASE_PROTOCOL_VERSION_V1 0x10000
|
||||||
|
#define BASE_PROTOCOL_VERSION_V2 0x20000
|
||||||
|
|
||||||
#define NUM_PROTOCOL_MASK 0xFFU
|
#define NUM_PROTOCOL_MASK 0xFFU
|
||||||
#define NUM_AGENT_MASK 0xFFU
|
#define NUM_AGENT_MASK 0xFFU
|
||||||
@@ -158,11 +159,10 @@ typedef struct _SCMI_BASE_PROTOCOL {
|
|||||||
|
|
||||||
// SCMI Message IDs for Base protocol.
|
// SCMI Message IDs for Base protocol.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_VENDOR = 0x3,
|
ScmiMessageIdBaseDiscoverVendor = 0x3,
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_SUB_VENDOR = 0x4,
|
ScmiMessageIdBaseDiscoverSubVendor = 0x4,
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_IMPLEMENTATION_VERSION = 0x5,
|
ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
|
||||||
SCMI_MESSAGE_ID_BASE_DISCOVER_LIST_PROTOCOLS = 0x6
|
ScmiMessageIdBaseDiscoverListProtocols = 0x6
|
||||||
} SCMI_MESSAGE_ID_BASE;
|
} SCMI_MESSAGE_ID_BASE;
|
||||||
|
|
||||||
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
|
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
|
||||||
|
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -89,10 +89,10 @@ EFI_STATUS
|
|||||||
@param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance.
|
@param[in] This A pointer to SCMI_CLOCK2_PROTOCOL Instance.
|
||||||
@param[in] ClockId Identifier for the clock device.
|
@param[in] ClockId Identifier for the clock device.
|
||||||
|
|
||||||
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
|
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
|
||||||
supports range of clock rates which are non-linear.
|
supports range of clock rates which are non-linear.
|
||||||
|
|
||||||
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
|
ScmiClockRateFormatLinear: Clock device supports
|
||||||
range of linear clock rates from Min to Max in steps.
|
range of linear clock rates from Min to Max in steps.
|
||||||
|
|
||||||
@param[out] TotalRates Total number of rates.
|
@param[out] TotalRates Total number of rates.
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -22,16 +22,16 @@ extern EFI_GUID gArmScmiClockProtocolGuid;
|
|||||||
|
|
||||||
// Message Type for clock management protocol.
|
// Message Type for clock management protocol.
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_MESSAGE_ID_CLOCK_ATTRIBUTES = 0x3,
|
ScmiMessageIdClockAttributes = 0x3,
|
||||||
SCMI_MESSAGE_ID_CLOCK_DESCRIBE_RATES = 0x4,
|
ScmiMessageIdClockDescribeRates = 0x4,
|
||||||
SCMI_MESSAGE_ID_CLOCK_RATE_SET = 0x5,
|
ScmiMessageIdClockRateSet = 0x5,
|
||||||
SCMI_MESSAGE_ID_CLOCK_RATE_GET = 0x6,
|
ScmiMessageIdClockRateGet = 0x6,
|
||||||
SCMI_MESSAGE_ID_CLOCK_CONFIG_SET = 0x7
|
ScmiMessageIdClockConfigSet = 0x7
|
||||||
} SCMI_MESSAGE_ID_CLOCK;
|
} SCMI_MESSAGE_ID_CLOCK;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_CLOCK_RATE_FORMAT_DISCRETE, // Non-linear range.
|
ScmiClockRateFormatDiscrete, // Non-linear range.
|
||||||
SCMI_CLOCK_RATE_FORMAT_LINEAR // Linear range.
|
ScmiClockRateFormatLinear // Linear range.
|
||||||
} SCMI_CLOCK_RATE_FORMAT;
|
} SCMI_CLOCK_RATE_FORMAT;
|
||||||
|
|
||||||
// Clock management protocol version.
|
// Clock management protocol version.
|
||||||
@@ -57,12 +57,18 @@ typedef enum {
|
|||||||
either Rate or Min/Max/Step triplet is valid.
|
either Rate or Min/Max/Step triplet is valid.
|
||||||
*/
|
*/
|
||||||
typedef struct {
|
typedef struct {
|
||||||
union {
|
|
||||||
UINT64 Min;
|
UINT64 Min;
|
||||||
UINT64 Rate;
|
|
||||||
};
|
|
||||||
UINT64 Max;
|
UINT64 Max;
|
||||||
UINT64 Step;
|
UINT64 Step;
|
||||||
|
} SCMI_CLOCK_RATE_CONTINUOUS;
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
UINT64 Rate;
|
||||||
|
} SCMI_CLOCK_RATE_DISCRETE;
|
||||||
|
|
||||||
|
typedef union {
|
||||||
|
SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
|
||||||
|
SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
|
||||||
} SCMI_CLOCK_RATE;
|
} SCMI_CLOCK_RATE;
|
||||||
|
|
||||||
#pragma pack()
|
#pragma pack()
|
||||||
@@ -133,10 +139,10 @@ EFI_STATUS
|
|||||||
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
|
@param[in] This A pointer to SCMI_CLOCK_PROTOCOL Instance.
|
||||||
@param[in] ClockId Identifier for the clock device.
|
@param[in] ClockId Identifier for the clock device.
|
||||||
|
|
||||||
@param[out] Format SCMI_CLOCK_RATE_FORMAT_DISCRETE: Clock device
|
@param[out] Format ScmiClockRateFormatDiscrete: Clock device
|
||||||
supports range of clock rates which are non-linear.
|
supports range of clock rates which are non-linear.
|
||||||
|
|
||||||
SCMI_CLOCK_RATE_FORMAT_LINEAR: Clock device supports
|
ScmiClockRateFormatLinear: Clock device supports
|
||||||
range of linear clock rates from Min to Max in steps.
|
range of linear clock rates from Min to Max in steps.
|
||||||
|
|
||||||
@param[out] TotalRates Total number of rates.
|
@param[out] TotalRates Total number of rates.
|
||||||
|
@@ -1,6 +1,6 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2017-2018, Arm Limited. All rights reserved.
|
Copyright (c) 2017-2021, Arm Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -247,12 +247,12 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL {
|
|||||||
} SCMI_PERFORMANCE_PROTOCOL;
|
} SCMI_PERFORMANCE_PROTOCOL;
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_DOMAIN_ATTRIBUTES = 0x3,
|
ScmiMessageIdPerformanceDomainAttributes = 0x3,
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_DESCRIBE_LEVELS = 0x4,
|
ScmiMessageIdPerformanceDescribeLevels = 0x4,
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_SET = 0x5,
|
ScmiMessageIdPerformanceLimitsSet = 0x5,
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_LIMITS_GET = 0x6,
|
ScmiMessageIdPerformanceLimitsGet = 0x6,
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_SET = 0x7,
|
ScmiMessageIdPerformanceLevelSet = 0x7,
|
||||||
SCMI_MESSAGE_ID_PERFORMANCE_LEVEL_GET = 0x8,
|
ScmiMessageIdPerformanceLevelGet = 0x8,
|
||||||
} SCMI_MESSAGE_ID_PERFORMANCE;
|
} SCMI_MESSAGE_ID_PERFORMANCE;
|
||||||
|
|
||||||
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */
|
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */
|
||||||
|
@@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
Generic ARM implementation of TimerLib.h
|
Generic ARM implementation of TimerLib.h
|
||||||
|
|
||||||
Copyright (c) 2011-2016, ARM Limited. All rights reserved.
|
Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -20,9 +20,9 @@
|
|||||||
|
|
||||||
// Select appropriate multiply function for platform architecture.
|
// Select appropriate multiply function for platform architecture.
|
||||||
#ifdef MDE_CPU_ARM
|
#ifdef MDE_CPU_ARM
|
||||||
#define MultU64xN MultU64x32
|
#define MULT_U64_X_N MultU64x32
|
||||||
#else
|
#else
|
||||||
#define MultU64xN MultU64x64
|
#define MULT_U64_X_N MultU64x64
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
@@ -56,7 +56,7 @@ TimerConstructor (
|
|||||||
// If the security extension is not implemented, set Timer Frequency
|
// If the security extension is not implemented, set Timer Frequency
|
||||||
// here.
|
// here.
|
||||||
//
|
//
|
||||||
if ((ArmReadIdPfr1 () & ARM_PFR1_SEC) == 0x0) {
|
if (ArmHasSecurityExtensions ()) {
|
||||||
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@@ -121,7 +121,7 @@ MicroSecondDelay (
|
|||||||
// = MicroSeconds x TICKS_PER_MICRO_SEC
|
// = MicroSeconds x TICKS_PER_MICRO_SEC
|
||||||
// = MicroSeconds x Frequency.10^-6
|
// = MicroSeconds x Frequency.10^-6
|
||||||
TimerTicks64 = DivU64x32 (
|
TimerTicks64 = DivU64x32 (
|
||||||
MultU64xN (
|
MULT_U64_X_N (
|
||||||
MicroSeconds,
|
MicroSeconds,
|
||||||
GetPlatformTimerFreq ()
|
GetPlatformTimerFreq ()
|
||||||
),
|
),
|
||||||
@@ -263,7 +263,7 @@ GetTimeInNanoSecond (
|
|||||||
// Time = --------- x 1,000,000,000
|
// Time = --------- x 1,000,000,000
|
||||||
// Frequency
|
// Frequency
|
||||||
//
|
//
|
||||||
NanoSeconds = MultU64xN (
|
NanoSeconds = MULT_U64_X_N (
|
||||||
DivU64x32Remainder (
|
DivU64x32Remainder (
|
||||||
Ticks,
|
Ticks,
|
||||||
TimerFreq,
|
TimerFreq,
|
||||||
@@ -276,7 +276,7 @@ GetTimeInNanoSecond (
|
|||||||
// will not overflow 64-bit.
|
// will not overflow 64-bit.
|
||||||
//
|
//
|
||||||
NanoSeconds += DivU64x32 (
|
NanoSeconds += DivU64x32 (
|
||||||
MultU64xN (
|
MULT_U64_X_N (
|
||||||
(UINT64) Remainder,
|
(UINT64) Remainder,
|
||||||
1000000000U),
|
1000000000U),
|
||||||
TimerFreq
|
TimerFreq
|
||||||
|
@@ -1,7 +1,7 @@
|
|||||||
/** @file
|
/** @file
|
||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -20,11 +20,14 @@ CacheRangeOperation (
|
|||||||
IN UINTN LineLength
|
IN UINTN LineLength
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINTN ArmCacheLineAlignmentMask = LineLength - 1;
|
UINTN ArmCacheLineAlignmentMask;
|
||||||
|
|
||||||
// Align address (rounding down)
|
// Align address (rounding down)
|
||||||
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
|
UINTN AlignedAddress;
|
||||||
UINTN EndAddress = (UINTN)Start + Length;
|
UINTN EndAddress;
|
||||||
|
|
||||||
|
ArmCacheLineAlignmentMask = LineLength - 1;
|
||||||
|
AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
|
||||||
|
EndAddress = (UINTN)Start + Length;
|
||||||
|
|
||||||
// Perform the line operation on an address in each cache line
|
// Perform the line operation on an address in each cache line
|
||||||
while (AlignedAddress < EndAddress) {
|
while (AlignedAddress < EndAddress) {
|
||||||
|
@@ -2,6 +2,7 @@
|
|||||||
Default exception handler
|
Default exception handler
|
||||||
|
|
||||||
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -70,7 +71,7 @@ CHAR8 *gLdmStack[] = {
|
|||||||
|
|
||||||
|
|
||||||
#define SIGN(_U) ((_U) ? "" : "-")
|
#define SIGN(_U) ((_U) ? "" : "-")
|
||||||
#define WRITE(_W) ((_W) ? "!" : "")
|
#define WRITE(_Write) ((_Write) ? "!" : "")
|
||||||
#define BYTE(_B) ((_B) ? "B":"")
|
#define BYTE(_B) ((_B) ? "B":"")
|
||||||
#define USER(_B) ((_B) ? "^" : "")
|
#define USER(_B) ((_B) ? "^" : "")
|
||||||
|
|
||||||
@@ -157,22 +158,25 @@ DisassembleArmInstruction (
|
|||||||
IN BOOLEAN Extended
|
IN BOOLEAN Extended
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINT32 OpCode = **OpCodePtr;
|
UINT32 OpCode;
|
||||||
CHAR8 *Type, *Root;
|
CHAR8 *Type;
|
||||||
BOOLEAN I, P, U, B, W, L, S, H;
|
CHAR8 *Root;
|
||||||
|
BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
|
||||||
UINT32 Rn, Rd, Rm;
|
UINT32 Rn, Rd, Rm;
|
||||||
UINT32 imode, offset_8, offset_12;
|
UINT32 IMod, Offset8, Offset12;
|
||||||
UINT32 Index;
|
UINT32 Index;
|
||||||
UINT32 shift_imm, shift;
|
UINT32 ShiftImm, Shift;
|
||||||
|
|
||||||
I = (OpCode & BIT25) == BIT25;
|
OpCode = **OpCodePtr;
|
||||||
P = (OpCode & BIT24) == BIT24;
|
|
||||||
U = (OpCode & BIT23) == BIT23;
|
Imm = (OpCode & BIT25) == BIT25; // I
|
||||||
B = (OpCode & BIT22) == BIT22; // Also called S
|
Pre = (OpCode & BIT24) == BIT24; // P
|
||||||
W = (OpCode & BIT21) == BIT21;
|
Up = (OpCode & BIT23) == BIT23; // U
|
||||||
L = (OpCode & BIT20) == BIT20;
|
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
|
||||||
S = (OpCode & BIT6) == BIT6;
|
Write = (OpCode & BIT21) == BIT21; // W
|
||||||
H = (OpCode & BIT5) == BIT5;
|
Load = (OpCode & BIT20) == BIT20; // L
|
||||||
|
Sign = (OpCode & BIT6) == BIT6; // S
|
||||||
|
Half = (OpCode & BIT5) == BIT5; // H
|
||||||
Rn = (OpCode >> 16) & 0xf;
|
Rn = (OpCode >> 16) & 0xf;
|
||||||
Rd = (OpCode >> 12) & 0xf;
|
Rd = (OpCode >> 12) & 0xf;
|
||||||
Rm = (OpCode & 0xf);
|
Rm = (OpCode & 0xf);
|
||||||
@@ -186,7 +190,7 @@ DisassembleArmInstruction (
|
|||||||
|
|
||||||
// LDREX, STREX
|
// LDREX, STREX
|
||||||
if ((OpCode & 0x0fe000f0) == 0x01800090) {
|
if ((OpCode & 0x0fe000f0) == 0x01800090) {
|
||||||
if (L) {
|
if (Load) {
|
||||||
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
|
// A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
|
||||||
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
|
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
|
||||||
} else {
|
} else {
|
||||||
@@ -198,89 +202,89 @@ DisassembleArmInstruction (
|
|||||||
|
|
||||||
// LDM/STM
|
// LDM/STM
|
||||||
if ((OpCode & 0x0e000000) == 0x08000000) {
|
if ((OpCode & 0x0e000000) == 0x08000000) {
|
||||||
if (L) {
|
if (Load) {
|
||||||
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
|
// A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
|
||||||
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
|
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
|
||||||
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
|
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
|
||||||
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
|
AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
|
||||||
} else {
|
} else {
|
||||||
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
|
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
|
||||||
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
|
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
|
||||||
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
|
AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
// LDR/STR Address Mode 2
|
// LDR/STR Address Mode 2
|
||||||
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
|
if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
|
||||||
offset_12 = OpCode & 0xfff;
|
Offset12 = OpCode & 0xfff;
|
||||||
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
|
if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
|
||||||
Index = AsciiSPrint (Buf, Size, "PLD");
|
Index = AsciiSPrint (Buf, Size, "PLD");
|
||||||
} else {
|
} else {
|
||||||
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", L ? "LDR" : "STR", COND (OpCode), BYTE (B), (!(P) && W) ? "T":"", gReg[Rd]);
|
Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
|
||||||
}
|
}
|
||||||
if (P) {
|
if (Pre) {
|
||||||
if (!I) {
|
if (!Imm) {
|
||||||
// A5.2.2 [<Rn>, #+/-<offset_12>]
|
// A5.2.2 [<Rn>, #+/-<offset_12>]
|
||||||
// A5.2.5 [<Rn>, #+/-<offset_12>]
|
// A5.2.5 [<Rn>, #+/-<offset_12>]
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (U), offset_12, WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x]%a", gReg[Rn], SIGN (Up), Offset12, WRITE (Write));
|
||||||
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
|
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
|
||||||
// A5.2.3 [<Rn>, +/-<Rm>]
|
// A5.2.3 [<Rn>, +/-<Rm>]
|
||||||
// A5.2.6 [<Rn>, +/-<Rm>]!
|
// A5.2.6 [<Rn>, +/-<Rm>]!
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (U), WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a]%a", gReg[Rn], SIGN (Up), WRITE (Write));
|
||||||
} else {
|
} else {
|
||||||
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
|
// A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
|
||||||
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
|
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
|
||||||
shift_imm = (OpCode >> 7) & 0x1f;
|
ShiftImm = (OpCode >> 7) & 0x1f;
|
||||||
shift = (OpCode >> 5) & 0x3;
|
Shift = (OpCode >> 5) & 0x3;
|
||||||
if (shift == 0x0) {
|
if (Shift == 0x0) {
|
||||||
Type = "LSL";
|
Type = "LSL";
|
||||||
} else if (shift == 0x1) {
|
} else if (Shift == 0x1) {
|
||||||
Type = "LSR";
|
Type = "LSR";
|
||||||
if (shift_imm == 0) {
|
if (ShiftImm == 0) {
|
||||||
shift_imm = 32;
|
ShiftImm = 32;
|
||||||
}
|
}
|
||||||
} else if (shift == 0x12) {
|
} else if (Shift == 0x2) {
|
||||||
Type = "ASR";
|
Type = "ASR";
|
||||||
} else if (shift_imm == 0) {
|
} else if (ShiftImm == 0) {
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
Type = "ROR";
|
Type = "ROR";
|
||||||
}
|
}
|
||||||
|
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
|
||||||
}
|
}
|
||||||
} else { // !P
|
} else { // !Pre
|
||||||
if (!I) {
|
if (!Imm) {
|
||||||
// A5.2.8 [<Rn>], #+/-<offset_12>
|
// A5.2.8 [<Rn>], #+/-<offset_12>
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (U), offset_12);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
|
||||||
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
|
} else if ((OpCode & 0x03000ff0) == 0x03000000) {
|
||||||
// A5.2.9 [<Rn>], +/-<Rm>
|
// A5.2.9 [<Rn>], +/-<Rm>
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
|
||||||
} else {
|
} else {
|
||||||
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
|
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
|
||||||
shift_imm = (OpCode >> 7) & 0x1f;
|
ShiftImm = (OpCode >> 7) & 0x1f;
|
||||||
shift = (OpCode >> 5) & 0x3;
|
Shift = (OpCode >> 5) & 0x3;
|
||||||
|
|
||||||
if (shift == 0x0) {
|
if (Shift == 0x0) {
|
||||||
Type = "LSL";
|
Type = "LSL";
|
||||||
} else if (shift == 0x1) {
|
} else if (Shift == 0x1) {
|
||||||
Type = "LSR";
|
Type = "LSR";
|
||||||
if (shift_imm == 0) {
|
if (ShiftImm == 0) {
|
||||||
shift_imm = 32;
|
ShiftImm = 32;
|
||||||
}
|
}
|
||||||
} else if (shift == 0x12) {
|
} else if (Shift == 0x2) {
|
||||||
Type = "ASR";
|
Type = "ASR";
|
||||||
} else if (shift_imm == 0) {
|
} else if (ShiftImm == 0) {
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (U), gReg[Rm]);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, RRX", gReg[Rn], SIGN (Up), gReg[Rm]);
|
||||||
// FIx me
|
// FIx me
|
||||||
return;
|
return;
|
||||||
} else {
|
} else {
|
||||||
Type = "ROR";
|
Type = "ROR";
|
||||||
}
|
}
|
||||||
|
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
@@ -289,18 +293,18 @@ DisassembleArmInstruction (
|
|||||||
if ((OpCode & 0x0e000000) == 0x00000000) {
|
if ((OpCode & 0x0e000000) == 0x00000000) {
|
||||||
// LDR/STR address mode 3
|
// LDR/STR address mode 3
|
||||||
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
|
// LDR|STR{<cond>}H|SH|SB|D <Rd>, <addressing_mode>
|
||||||
if (L) {
|
if (Load) {
|
||||||
if (!S) {
|
if (!Sign) {
|
||||||
Root = "LDR%aH %a, ";
|
Root = "LDR%aH %a, ";
|
||||||
} else if (!H) {
|
} else if (!Half) {
|
||||||
Root = "LDR%aSB %a, ";
|
Root = "LDR%aSB %a, ";
|
||||||
} else {
|
} else {
|
||||||
Root = "LDR%aSH %a, ";
|
Root = "LDR%aSH %a, ";
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (!S) {
|
if (!Sign) {
|
||||||
Root = "STR%aH %a ";
|
Root = "STR%aH %a ";
|
||||||
} else if (!H) {
|
} else if (!Half) {
|
||||||
Root = "LDR%aD %a ";
|
Root = "LDR%aD %a ";
|
||||||
} else {
|
} else {
|
||||||
Root = "STR%aD %a ";
|
Root = "STR%aD %a ";
|
||||||
@@ -309,28 +313,28 @@ DisassembleArmInstruction (
|
|||||||
|
|
||||||
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
|
Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
|
||||||
|
|
||||||
S = (OpCode & BIT6) == BIT6;
|
Sign = (OpCode & BIT6) == BIT6;
|
||||||
H = (OpCode & BIT5) == BIT5;
|
Half = (OpCode & BIT5) == BIT5;
|
||||||
offset_8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
|
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
|
||||||
if (P & !W) {
|
if (Pre & !Write) {
|
||||||
// Immediate offset/index
|
// Immediate offset/index
|
||||||
if (B) {
|
if (WriteBack) {
|
||||||
// A5.3.2 [<Rn>, #+/-<offset_8>]
|
// A5.3.2 [<Rn>, #+/-<offset_8>]
|
||||||
// A5.3.4 [<Rn>, #+/-<offset_8>]!
|
// A5.3.4 [<Rn>, #+/-<offset_8>]!
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (U), offset_8, WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
|
||||||
} else {
|
} else {
|
||||||
// A5.3.3 [<Rn>, +/-<Rm>]
|
// A5.3.3 [<Rn>, +/-<Rm>]
|
||||||
// A5.3.5 [<Rn>, +/-<Rm>]!
|
// A5.3.5 [<Rn>, +/-<Rm>]!
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
// Register offset/index
|
// Register offset/index
|
||||||
if (B) {
|
if (WriteBack) {
|
||||||
// A5.3.6 [<Rn>], #+/-<offset_8>
|
// A5.3.6 [<Rn>], #+/-<offset_8>
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (U), offset_8);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
|
||||||
} else {
|
} else {
|
||||||
// A5.3.7 [<Rn>], +/-<Rm>
|
// A5.3.7 [<Rn>], +/-<Rm>
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (U), gReg[Rm]);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
@@ -339,19 +343,19 @@ DisassembleArmInstruction (
|
|||||||
if ((OpCode & 0x0fb000f0) == 0x01000050) {
|
if ((OpCode & 0x0fb000f0) == 0x01000050) {
|
||||||
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
// A4.1.108 SWP SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
||||||
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
// A4.1.109 SWPB SWP{<cond>}B <Rd>, <Rm>, [<Rn>]
|
||||||
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (B), gReg[Rd], gReg[Rm], gReg[Rn]);
|
AsciiSPrint (Buf, Size, "SWP%a%a %a, %a, [%a]", COND (OpCode), BYTE (WriteBack), gReg[Rd], gReg[Rm], gReg[Rn]);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
|
if ((OpCode & 0xfe5f0f00) == 0xf84d0500) {
|
||||||
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
|
// A4.1.90 SRS SRS<addressing_mode> #<mode>{!}
|
||||||
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (W));
|
AsciiSPrint (Buf, Size, "SRS%a #0x%x%a", gLdmStack[(OpCode >> 23) & 3], OpCode & 0x1f, WRITE (Write));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((OpCode & 0xfe500f00) == 0xf8100500) {
|
if ((OpCode & 0xfe500f00) == 0xf8100500) {
|
||||||
// A4.1.59 RFE<addressing_mode> <Rn>{!}
|
// A4.1.59 RFE<addressing_mode> <Rn>{!}
|
||||||
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (W));
|
AsciiSPrint (Buf, Size, "RFE%a %a", gLdmStack[(OpCode >> 23) & 3], gReg[Rn], WRITE (Write));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -366,8 +370,12 @@ DisassembleArmInstruction (
|
|||||||
if (((OpCode >> 6) & 0x7) == 0) {
|
if (((OpCode >> 6) & 0x7) == 0) {
|
||||||
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
|
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
|
||||||
} else {
|
} else {
|
||||||
imode = (OpCode >> 18) & 0x3;
|
IMod = (OpCode >> 18) & 0x3;
|
||||||
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a", (imode == 3) ? "ID":"IE", (OpCode & BIT8) ? "A":"", (OpCode & BIT7) ? "I":"", (OpCode & BIT6) ? "F":"");
|
Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
|
||||||
|
(IMod == 3) ? "ID":"IE",
|
||||||
|
((OpCode & BIT8) != 0) ? "A":"",
|
||||||
|
((OpCode & BIT7) != 0) ? "I":"",
|
||||||
|
((OpCode & BIT6) != 0) ? "F":"");
|
||||||
if ((OpCode & BIT17) != 0) {
|
if ((OpCode & BIT17) != 0) {
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
|
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
|
||||||
}
|
}
|
||||||
@@ -383,19 +391,19 @@ DisassembleArmInstruction (
|
|||||||
|
|
||||||
if ((OpCode & 0x0fb00000) == 0x01000000) {
|
if ((OpCode & 0x0fb00000) == 0x01000000) {
|
||||||
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
|
// A4.1.38 MRS{<cond>} <Rd>, CPSR MRS{<cond>} <Rd>, SPSR
|
||||||
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], B ? "SPSR" : "CPSR");
|
AsciiSPrint (Buf, Size, "MRS%a %a, %a", COND (OpCode), gReg[Rd], WriteBack ? "SPSR" : "CPSR");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
if ((OpCode & 0x0db00000) == 0x01200000) {
|
if ((OpCode & 0x0db00000) == 0x01200000) {
|
||||||
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
|
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
|
||||||
if (I) {
|
if (Imm) {
|
||||||
// MSR{<cond>} CPSR_<fields>, #<immediate>
|
// MSR{<cond>} CPSR_<fields>, #<immediate>
|
||||||
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), B ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
|
AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
|
||||||
} else {
|
} else {
|
||||||
// MSR{<cond>} CPSR_<fields>, <Rm>
|
// MSR{<cond>} CPSR_<fields>, <Rm>
|
||||||
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), B ? "SPSR" : "CPSR", gReg[Rd]);
|
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@@ -409,35 +417,35 @@ DisassembleArmInstruction (
|
|||||||
if ((OpCode & 0x0e000000) == 0x0c000000) {
|
if ((OpCode & 0x0e000000) == 0x0c000000) {
|
||||||
// A4.1.19 LDC and A4.1.96 SDC
|
// A4.1.19 LDC and A4.1.96 SDC
|
||||||
if ((OpCode & 0xf0000000) == 0xf0000000) {
|
if ((OpCode & 0xf0000000) == 0xf0000000) {
|
||||||
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", L ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
|
Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
|
||||||
} else {
|
} else {
|
||||||
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", L ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
|
Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!P) {
|
if (!Pre) {
|
||||||
if (!W) {
|
if (!Write) {
|
||||||
// A5.5.5.5 [<Rn>], <option>
|
// A5.5.5.5 [<Rn>], <option>
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
|
||||||
} else {
|
} else {
|
||||||
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
|
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (U), OpCode & 0xff);
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
|
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
|
||||||
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (U), OpCode & 0xff, WRITE (W));
|
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((OpCode & 0x0f000010) == 0x0e000010) {
|
if ((OpCode & 0x0f000010) == 0x0e000010) {
|
||||||
// A4.1.32 MRC2, MCR2
|
// A4.1.32 MRC2, MCR2
|
||||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", L ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((OpCode & 0x0ff00000) == 0x0c400000) {
|
if ((OpCode & 0x0ff00000) == 0x0c400000) {
|
||||||
// A4.1.33 MRRC2, MCRR2
|
// A4.1.33 MRRC2, MCRR2
|
||||||
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", L ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@@ -9,6 +9,7 @@
|
|||||||
try to reuse existing case entries if possible.
|
try to reuse existing case entries if possible.
|
||||||
|
|
||||||
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -451,7 +452,7 @@ SignExtend32 (
|
|||||||
// in the instruction address and you get back the aligned answer
|
// in the instruction address and you get back the aligned answer
|
||||||
//
|
//
|
||||||
UINT32
|
UINT32
|
||||||
PCAlign4 (
|
PcAlign4 (
|
||||||
IN UINT32 Data
|
IN UINT32 Data
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
@@ -486,12 +487,19 @@ DisassembleThumbInstruction (
|
|||||||
UINT32 Index;
|
UINT32 Index;
|
||||||
UINT32 Offset;
|
UINT32 Offset;
|
||||||
UINT16 Rd, Rn, Rm, Rt, Rt2;
|
UINT16 Rd, Rn, Rm, Rt, Rt2;
|
||||||
BOOLEAN H1, H2, imod;
|
BOOLEAN H1Bit; // H1
|
||||||
|
BOOLEAN H2Bit; // H2
|
||||||
|
BOOLEAN IMod; // imod
|
||||||
//BOOLEAN ItFlag;
|
//BOOLEAN ItFlag;
|
||||||
UINT32 PC, Target, msbit, lsbit;
|
UINT32 Pc, Target, MsBit, LsBit;
|
||||||
CHAR8 *Cond;
|
CHAR8 *Cond;
|
||||||
BOOLEAN S, J1, J2, P, U, W;
|
BOOLEAN Sign; // S
|
||||||
UINT32 coproc, opc1, opc2, CRd, CRn, CRm;
|
BOOLEAN J1Bit; // J1
|
||||||
|
BOOLEAN J2Bit; // J2
|
||||||
|
BOOLEAN Pre; // P
|
||||||
|
BOOLEAN UAdd; // U
|
||||||
|
BOOLEAN WriteBack; // W
|
||||||
|
UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
|
||||||
UINT32 Mask;
|
UINT32 Mask;
|
||||||
|
|
||||||
OpCodePtr = *OpCodePtrPtr;
|
OpCodePtr = *OpCodePtrPtr;
|
||||||
@@ -504,10 +512,10 @@ DisassembleThumbInstruction (
|
|||||||
Rd = OpCode & 0x7;
|
Rd = OpCode & 0x7;
|
||||||
Rn = (OpCode >> 3) & 0x7;
|
Rn = (OpCode >> 3) & 0x7;
|
||||||
Rm = (OpCode >> 6) & 0x7;
|
Rm = (OpCode >> 6) & 0x7;
|
||||||
H1 = (OpCode & BIT7) != 0;
|
H1Bit = (OpCode & BIT7) != 0;
|
||||||
H2 = (OpCode & BIT6) != 0;
|
H2Bit = (OpCode & BIT6) != 0;
|
||||||
imod = (OpCode & BIT4) != 0;
|
IMod = (OpCode & BIT4) != 0;
|
||||||
PC = (UINT32)(UINTN)OpCodePtr;
|
Pc = (UINT32)(UINTN)OpCodePtr;
|
||||||
|
|
||||||
// Increment by the minimum instruction size, Thumb2 could be bigger
|
// Increment by the minimum instruction size, Thumb2 could be bigger
|
||||||
*OpCodePtrPtr += 1;
|
*OpCodePtrPtr += 1;
|
||||||
@@ -548,7 +556,7 @@ DisassembleThumbInstruction (
|
|||||||
case LOAD_STORE_FORMAT3:
|
case LOAD_STORE_FORMAT3:
|
||||||
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
|
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]
|
||||||
Target = (OpCode & 0xff) << 2;
|
Target = (OpCode & 0xff) << 2;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
|
||||||
return;
|
return;
|
||||||
case LOAD_STORE_FORMAT4:
|
case LOAD_STORE_FORMAT4:
|
||||||
// Rt, [SP, #imm8]
|
// Rt, [SP, #imm8]
|
||||||
@@ -583,16 +591,16 @@ DisassembleThumbInstruction (
|
|||||||
Cond = gCondition[(OpCode >> 8) & 0xf];
|
Cond = gCondition[(OpCode >> 8) & 0xf];
|
||||||
Buf[Offset-5] = *Cond++;
|
Buf[Offset-5] = *Cond++;
|
||||||
Buf[Offset-4] = *Cond;
|
Buf[Offset-4] = *Cond;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
|
||||||
return;
|
return;
|
||||||
case UNCONDITIONAL_BRANCH_SHORT:
|
case UNCONDITIONAL_BRANCH_SHORT:
|
||||||
// A6.3.2 B <target_address>
|
// A6.3.2 B <target_address>
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case BRANCH_EXCHANGE:
|
case BRANCH_EXCHANGE:
|
||||||
// A6.3.3 BX|BLX <Rm>
|
// A6.3.3 BX|BLX <Rm>
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case DATA_FORMAT1:
|
case DATA_FORMAT1:
|
||||||
@@ -629,12 +637,12 @@ DisassembleThumbInstruction (
|
|||||||
return;
|
return;
|
||||||
case DATA_FORMAT8:
|
case DATA_FORMAT8:
|
||||||
// A6.4.3 <Rd>|<Rn>, <Rm>
|
// A6.4.3 <Rd>|<Rn>, <Rm>
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case CPS_FORMAT:
|
case CPS_FORMAT:
|
||||||
// A7.1.24
|
// A7.1.24
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case ENDIAN_FORMAT:
|
case ENDIAN_FORMAT:
|
||||||
@@ -645,13 +653,13 @@ DisassembleThumbInstruction (
|
|||||||
case DATA_CBZ:
|
case DATA_CBZ:
|
||||||
// CB{N}Z <Rn>, <Lable>
|
// CB{N}Z <Rn>, <Lable>
|
||||||
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
|
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case ADR_FORMAT:
|
case ADR_FORMAT:
|
||||||
// ADR <Rd>, <Label>
|
// ADR <Rd>, <Label>
|
||||||
Target = (OpCode & 0xff) << 2;
|
Target = (OpCode & 0xff) << 2;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case IT_BLOCK:
|
case IT_BLOCK:
|
||||||
@@ -708,32 +716,32 @@ DisassembleThumbInstruction (
|
|||||||
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
|
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
|
||||||
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
|
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
|
||||||
Target = SignExtend32 (Target, BIT20);
|
Target = SignExtend32 (Target, BIT20);
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
|
||||||
return;
|
return;
|
||||||
case B_T4:
|
case B_T4:
|
||||||
// S:I1:I2:imm10:imm11:0
|
// S:I1:I2:imm10:imm11:0
|
||||||
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
|
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
|
||||||
S = (OpCode32 & BIT26) == BIT26;
|
Sign = (OpCode32 & BIT26) == BIT26;
|
||||||
J1 = (OpCode32 & BIT13) == BIT13;
|
J1Bit = (OpCode32 & BIT13) == BIT13;
|
||||||
J2 = (OpCode32 & BIT11) == BIT11;
|
J2Bit = (OpCode32 & BIT11) == BIT11;
|
||||||
Target |= (!(J2 ^ S) ? BIT22 : 0); // I2
|
Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
|
||||||
Target |= (!(J1 ^ S) ? BIT23 : 0); // I1
|
Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
|
||||||
Target |= (S ? BIT24 : 0); // S
|
Target |= (Sign ? BIT24 : 0); // S
|
||||||
Target = SignExtend32 (Target, BIT24);
|
Target = SignExtend32 (Target, BIT24);
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case BL_T2:
|
case BL_T2:
|
||||||
// BLX S:I1:I2:imm10:imm11:0
|
// BLX S:I1:I2:imm10:imm11:0
|
||||||
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
|
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
|
||||||
S = (OpCode32 & BIT26) == BIT26;
|
Sign = (OpCode32 & BIT26) == BIT26;
|
||||||
J1 = (OpCode32 & BIT13) == BIT13;
|
J1Bit = (OpCode32 & BIT13) == BIT13;
|
||||||
J2 = (OpCode32 & BIT11) == BIT11;
|
J2Bit = (OpCode32 & BIT11) == BIT11;
|
||||||
Target |= (!(J2 ^ S) ? BIT23 : 0); // I2
|
Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
|
||||||
Target |= (!(J1 ^ S) ? BIT24 : 0); // I1
|
Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
|
||||||
Target |= (S ? BIT25 : 0); // S
|
Target |= (Sign ? BIT25 : 0); // S
|
||||||
Target = SignExtend32 (Target, BIT25);
|
Target = SignExtend32 (Target, BIT25);
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case POP_T2:
|
case POP_T2:
|
||||||
@@ -748,8 +756,8 @@ DisassembleThumbInstruction (
|
|||||||
|
|
||||||
case STM_FORMAT:
|
case STM_FORMAT:
|
||||||
// <Rn>{!}, <registers>
|
// <Rn>{!}, <registers>
|
||||||
W = (OpCode32 & BIT21) == BIT21;
|
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case LDM_REG_IMM12_SIGNED:
|
case LDM_REG_IMM12_SIGNED:
|
||||||
@@ -759,7 +767,7 @@ DisassembleThumbInstruction (
|
|||||||
// U == 0 means subtrack, U == 1 means add
|
// U == 0 means subtrack, U == 1 means add
|
||||||
Target = -Target;
|
Target = -Target;
|
||||||
}
|
}
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case LDM_REG_INDIRECT_LSL:
|
case LDM_REG_INDIRECT_LSL:
|
||||||
@@ -784,36 +792,36 @@ DisassembleThumbInstruction (
|
|||||||
|
|
||||||
case LDM_REG_IMM8:
|
case LDM_REG_IMM8:
|
||||||
// <rt>, [<rn>, {, #<imm8>}]{!}
|
// <rt>, [<rn>, {, #<imm8>}]{!}
|
||||||
W = (OpCode32 & BIT8) == BIT8;
|
WriteBack = (OpCode32 & BIT8) == BIT8;
|
||||||
U = (OpCode32 & BIT9) == BIT9;
|
UAdd = (OpCode32 & BIT9) == BIT9;
|
||||||
P = (OpCode32 & BIT10) == BIT10;
|
Pre = (OpCode32 & BIT10) == BIT10;
|
||||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
|
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
|
||||||
if (P) {
|
if (Pre) {
|
||||||
if ((OpCode32 & 0xff) == 0) {
|
if ((OpCode32 & 0xff) == 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
|
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
|
||||||
} else {
|
} else {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
|
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
|
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case LDRD_REG_IMM8_SIGNED:
|
case LDRD_REG_IMM8_SIGNED:
|
||||||
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
|
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
|
||||||
P = (OpCode32 & BIT24) == BIT24; // index = P
|
Pre = (OpCode32 & BIT24) == BIT24; // index = P
|
||||||
U = (OpCode32 & BIT23) == BIT23;
|
UAdd = (OpCode32 & BIT23) == BIT23;
|
||||||
W = (OpCode32 & BIT21) == BIT21;
|
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
|
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
|
||||||
if (P) {
|
if (Pre) {
|
||||||
if ((OpCode32 & 0xff) == 0) {
|
if ((OpCode32 & 0xff) == 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
|
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
|
||||||
} else {
|
} else {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");
|
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if ((OpCode32 & 0xff) != 0) {
|
if ((OpCode32 & 0xff) != 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);
|
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
@@ -825,7 +833,7 @@ DisassembleThumbInstruction (
|
|||||||
// U == 0 means subtrack, U == 1 means add
|
// U == 0 means subtrack, U == 1 means add
|
||||||
Target = -Target;
|
Target = -Target;
|
||||||
}
|
}
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case LDREXB:
|
case LDREXB:
|
||||||
@@ -840,14 +848,14 @@ DisassembleThumbInstruction (
|
|||||||
|
|
||||||
case SRS_FORMAT:
|
case SRS_FORMAT:
|
||||||
// SP{!}, #<mode>
|
// SP{!}, #<mode>
|
||||||
W = (OpCode32 & BIT21) == BIT21;
|
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case RFE_FORMAT:
|
case RFE_FORMAT:
|
||||||
// <Rn>{!}
|
// <Rn>{!}
|
||||||
W = (OpCode32 & BIT21) == BIT21;
|
WriteBack = (OpCode32 & BIT21) == BIT21;
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case ADD_IMM12:
|
case ADD_IMM12:
|
||||||
@@ -917,9 +925,9 @@ DisassembleThumbInstruction (
|
|||||||
// ADDR <Rd>, <label>
|
// ADDR <Rd>, <label>
|
||||||
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
|
||||||
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
|
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
|
||||||
Target = PCAlign4 (PC) - Target;
|
Target = PcAlign4 (Pc) - Target;
|
||||||
} else {
|
} else {
|
||||||
Target = PCAlign4 (PC) + Target;
|
Target = PcAlign4 (Pc) + Target;
|
||||||
}
|
}
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
|
||||||
return;
|
return;
|
||||||
@@ -932,52 +940,52 @@ DisassembleThumbInstruction (
|
|||||||
|
|
||||||
case BFC_THUMB2:
|
case BFC_THUMB2:
|
||||||
// BFI <Rd>, <Rn>, #<lsb>, #<width>
|
// BFI <Rd>, <Rn>, #<lsb>, #<width>
|
||||||
msbit = OpCode32 & 0x1f;
|
MsBit = OpCode32 & 0x1f;
|
||||||
lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
|
LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
|
||||||
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
|
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
|
||||||
// BFC <Rd>, #<lsb>, #<width>
|
// BFC <Rd>, #<lsb>, #<width>
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
|
||||||
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
|
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
|
||||||
} else {
|
} else {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);
|
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case CPD_THUMB2:
|
case CPD_THUMB2:
|
||||||
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
|
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
|
||||||
coproc = (OpCode32 >> 8) & 0xf;
|
Coproc = (OpCode32 >> 8) & 0xf;
|
||||||
opc1 = (OpCode32 >> 20) & 0xf;
|
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||||
opc2 = (OpCode32 >> 5) & 0x7;
|
Opc2 = (OpCode32 >> 5) & 0x7;
|
||||||
CRd = (OpCode32 >> 12) & 0xf;
|
CRd = (OpCode32 >> 12) & 0xf;
|
||||||
CRn = (OpCode32 >> 16) & 0xf;
|
CRn = (OpCode32 >> 16) & 0xf;
|
||||||
CRm = OpCode32 & 0xf;
|
CRm = OpCode32 & 0xf;
|
||||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);
|
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
|
||||||
if (opc2 != 0) {
|
if (Opc2 != 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case MRC_THUMB2:
|
case MRC_THUMB2:
|
||||||
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
|
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
|
||||||
coproc = (OpCode32 >> 8) & 0xf;
|
Coproc = (OpCode32 >> 8) & 0xf;
|
||||||
opc1 = (OpCode32 >> 20) & 0xf;
|
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||||
opc2 = (OpCode32 >> 5) & 0x7;
|
Opc2 = (OpCode32 >> 5) & 0x7;
|
||||||
CRn = (OpCode32 >> 16) & 0xf;
|
CRn = (OpCode32 >> 16) & 0xf;
|
||||||
CRm = OpCode32 & 0xf;
|
CRm = OpCode32 & 0xf;
|
||||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
|
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
|
||||||
if (opc2 != 0) {
|
if (Opc2 != 0) {
|
||||||
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
|
AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
|
||||||
}
|
}
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case MRRC_THUMB2:
|
case MRRC_THUMB2:
|
||||||
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
|
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
|
||||||
coproc = (OpCode32 >> 8) & 0xf;
|
Coproc = (OpCode32 >> 8) & 0xf;
|
||||||
opc1 = (OpCode32 >> 20) & 0xf;
|
Opc1 = (OpCode32 >> 20) & 0xf;
|
||||||
CRn = (OpCode32 >> 16) & 0xf;
|
CRn = (OpCode32 >> 16) & 0xf;
|
||||||
CRm = OpCode32 & 0xf;
|
CRm = OpCode32 & 0xf;
|
||||||
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
|
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case THUMB2_2REGS:
|
case THUMB2_2REGS:
|
||||||
|
@@ -2,6 +2,7 @@
|
|||||||
* Exception Handling support specific for AArch64
|
* Exception Handling support specific for AArch64
|
||||||
*
|
*
|
||||||
* Copyright (c) 2016 HP Development Company, L.P.
|
* Copyright (c) 2016 HP Development Company, L.P.
|
||||||
|
* Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
*
|
*
|
||||||
@@ -19,26 +20,25 @@ EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] =
|
|||||||
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
|
PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
|
||||||
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
|
UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
|
||||||
|
|
||||||
#define EL0_STACK_PAGES 2
|
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
|
||||||
|
STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
|
||||||
|
|
||||||
VOID
|
VOID
|
||||||
RegisterEl0Stack (
|
RegisterEl0Stack (
|
||||||
IN VOID *Stack
|
IN VOID *Stack
|
||||||
);
|
);
|
||||||
|
|
||||||
RETURN_STATUS ArchVectorConfig(
|
RETURN_STATUS
|
||||||
|
ArchVectorConfig (
|
||||||
IN UINTN VectorBaseAddress
|
IN UINTN VectorBaseAddress
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINTN HcrReg;
|
UINTN HcrReg;
|
||||||
UINT8 *Stack;
|
|
||||||
|
|
||||||
Stack = AllocatePages (EL0_STACK_PAGES);
|
// Round down sp by 16 bytes alignment
|
||||||
if (Stack == NULL) {
|
RegisterEl0Stack (
|
||||||
return RETURN_OUT_OF_RESOURCES;
|
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
|
||||||
}
|
);
|
||||||
|
|
||||||
RegisterEl0Stack ((UINT8 *)Stack + EFI_PAGES_TO_SIZE (EL0_STACK_PAGES));
|
|
||||||
|
|
||||||
if (ArmReadCurrentEL() == AARCH64_EL2) {
|
if (ArmReadCurrentEL() == AARCH64_EL2) {
|
||||||
HcrReg = ArmReadHcr();
|
HcrReg = ArmReadHcr();
|
||||||
|
@@ -1,5 +1,5 @@
|
|||||||
//
|
//
|
||||||
// Copyright (c) 2011 - 2014 ARM LTD. All rights reserved.<BR>
|
// Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
|
// Portion of Copyright (c) 2014 NVIDIA Corporation. All rights reserved.<BR>
|
||||||
// Copyright (c) 2016 HP Development Company, L.P.
|
// Copyright (c) 2016 HP Development Company, L.P.
|
||||||
//
|
//
|
||||||
@@ -200,19 +200,19 @@ ASM_PFX(SErrorSP0):
|
|||||||
//
|
//
|
||||||
// Current EL with SPx: 0x200 - 0x380
|
// Current EL with SPx: 0x200 - 0x380
|
||||||
//
|
//
|
||||||
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SYNC)
|
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SYNC)
|
||||||
ASM_PFX(SynchronousExceptionSPx):
|
ASM_PFX(SynchronousExceptionSPx):
|
||||||
ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
|
ExceptionEntry EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, SP0
|
||||||
|
|
||||||
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_IRQ)
|
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_IRQ)
|
||||||
ASM_PFX(IrqSPx):
|
ASM_PFX(IrqSPx):
|
||||||
ExceptionEntry EXCEPT_AARCH64_IRQ
|
ExceptionEntry EXCEPT_AARCH64_IRQ
|
||||||
|
|
||||||
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_FIQ)
|
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_FIQ)
|
||||||
ASM_PFX(FiqSPx):
|
ASM_PFX(FiqSPx):
|
||||||
ExceptionEntry EXCEPT_AARCH64_FIQ
|
ExceptionEntry EXCEPT_AARCH64_FIQ
|
||||||
|
|
||||||
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPx_SERR)
|
VECTOR_ENTRY(ExceptionHandlersStart, ARM_VECTOR_CUR_SPX_SERR)
|
||||||
ASM_PFX(SErrorSPx):
|
ASM_PFX(SErrorSPx):
|
||||||
ExceptionEntry EXCEPT_AARCH64_SERROR
|
ExceptionEntry EXCEPT_AARCH64_SERROR
|
||||||
|
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
* Exception handling support specific for ARM
|
* Exception handling support specific for ARM
|
||||||
*
|
*
|
||||||
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
* Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
|
* Copyright (c) 2014 - 2021, Arm Limited. All rights reserved.<BR>
|
||||||
* Copyright (c) 2016 HP Development Company, L.P.<BR>
|
* Copyright (c) 2016 HP Development Company, L.P.<BR>
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
@@ -26,7 +26,8 @@ PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNME
|
|||||||
// NOTE: This code assumes vectors are ARM and not Thumb code
|
// NOTE: This code assumes vectors are ARM and not Thumb code
|
||||||
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
|
UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
|
||||||
|
|
||||||
RETURN_STATUS ArchVectorConfig(
|
RETURN_STATUS
|
||||||
|
ArchVectorConfig (
|
||||||
IN UINTN VectorBaseAddress
|
IN UINTN VectorBaseAddress
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
@@ -2,7 +2,7 @@
|
|||||||
* Main file supporting the SEC Phase for Versatile Express
|
* Main file supporting the SEC Phase for Versatile Express
|
||||||
*
|
*
|
||||||
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
|
* Copyright (c) 2011-2021, Arm Limited. All rights reserved.<BR>
|
||||||
* Copyright (c) 2016 HP Development Company, L.P.
|
* Copyright (c) 2016 HP Development Company, L.P.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
@@ -253,7 +253,8 @@ RETURN_STATUS
|
|||||||
RegisterCpuInterruptHandler(
|
RegisterCpuInterruptHandler(
|
||||||
IN EFI_EXCEPTION_TYPE ExceptionType,
|
IN EFI_EXCEPTION_TYPE ExceptionType,
|
||||||
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
|
IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
|
||||||
) {
|
)
|
||||||
|
{
|
||||||
if (ExceptionType > gMaxExceptionNumber) {
|
if (ExceptionType > gMaxExceptionNumber) {
|
||||||
return RETURN_UNSUPPORTED;
|
return RETURN_UNSUPPORTED;
|
||||||
}
|
}
|
||||||
|
@@ -1,60 +0,0 @@
|
|||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2014, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
#include <Library/ArmGicLib.h>
|
|
||||||
|
|
||||||
STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
|
|
||||||
|
|
||||||
RETURN_STATUS
|
|
||||||
EFIAPI
|
|
||||||
ArmGicArchLibInitialize (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 IccSre;
|
|
||||||
|
|
||||||
// Ideally we would like to use the GICC IIDR Architecture version here, but
|
|
||||||
// this does not seem to be very reliable as the implementation could easily
|
|
||||||
// get it wrong. It is more reliable to check if the GICv3 System Register
|
|
||||||
// feature is implemented on the CPU. This is also convenient as our GICv3
|
|
||||||
// driver requires SRE. If only Memory mapped access is available we try to
|
|
||||||
// drive the GIC as a v2.
|
|
||||||
if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
|
|
||||||
// Make sure System Register access is enabled (SRE). This depends on the
|
|
||||||
// higher privilege level giving us permission, otherwise we will either
|
|
||||||
// cause an exception here, or the write doesn't stick in which case we need
|
|
||||||
// to fall back to the GICv2 MMIO interface.
|
|
||||||
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
|
|
||||||
// at the same exception level.
|
|
||||||
// It is the OS responsibility to set this bit.
|
|
||||||
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
|
|
||||||
if (!(IccSre & ICC_SRE_EL2_SRE)) {
|
|
||||||
ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
|
|
||||||
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
|
|
||||||
}
|
|
||||||
if (IccSre & ICC_SRE_EL2_SRE) {
|
|
||||||
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
|
|
||||||
|
|
||||||
Done:
|
|
||||||
return RETURN_SUCCESS;
|
|
||||||
}
|
|
||||||
|
|
||||||
ARM_GIC_ARCH_REVISION
|
|
||||||
EFIAPI
|
|
||||||
ArmGicGetSupportedArchRevision (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
return mGicArchRevision;
|
|
||||||
}
|
|
@@ -25,7 +25,7 @@ ArmGicArchLibInitialize (
|
|||||||
// feature is implemented on the CPU. This is also convenient as our GICv3
|
// feature is implemented on the CPU. This is also convenient as our GICv3
|
||||||
// driver requires SRE. If only Memory mapped access is available we try to
|
// driver requires SRE. If only Memory mapped access is available we try to
|
||||||
// drive the GIC as a v2.
|
// drive the GIC as a v2.
|
||||||
if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
|
if (ArmHasGicSystemRegisters ()) {
|
||||||
// Make sure System Register access is enabled (SRE). This depends on the
|
// Make sure System Register access is enabled (SRE). This depends on the
|
||||||
// higher privilege level giving us permission, otherwise we will either
|
// higher privilege level giving us permission, otherwise we will either
|
||||||
// cause an exception here, or the write doesn't stick in which case we need
|
// cause an exception here, or the write doesn't stick in which case we need
|
@@ -14,11 +14,8 @@
|
|||||||
LIBRARY_CLASS = ArmGicArchLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
|
LIBRARY_CLASS = ArmGicArchLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
|
||||||
CONSTRUCTOR = ArmGicArchLibInitialize
|
CONSTRUCTOR = ArmGicArchLibInitialize
|
||||||
|
|
||||||
[Sources.ARM]
|
[Sources]
|
||||||
Arm/ArmGicArchLib.c
|
ArmGicArchLib.c
|
||||||
|
|
||||||
[Sources.AARCH64]
|
|
||||||
AArch64/ArmGicArchLib.c
|
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
MdePkg/MdePkg.dec
|
MdePkg/MdePkg.dec
|
||||||
|
@@ -1,45 +0,0 @@
|
|||||||
/** @file
|
|
||||||
*
|
|
||||||
* Copyright (c) 2014, ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
|
|
||||||
#include <Library/ArmLib.h>
|
|
||||||
#include <Library/ArmGicLib.h>
|
|
||||||
|
|
||||||
ARM_GIC_ARCH_REVISION
|
|
||||||
EFIAPI
|
|
||||||
ArmGicGetSupportedArchRevision (
|
|
||||||
VOID
|
|
||||||
)
|
|
||||||
{
|
|
||||||
UINT32 IccSre;
|
|
||||||
|
|
||||||
// Ideally we would like to use the GICC IIDR Architecture version here, but
|
|
||||||
// this does not seem to be very reliable as the implementation could easily
|
|
||||||
// get it wrong. It is more reliable to check if the GICv3 System Register
|
|
||||||
// feature is implemented on the CPU. This is also convenient as our GICv3
|
|
||||||
// driver requires SRE. If only Memory mapped access is available we try to
|
|
||||||
// drive the GIC as a v2.
|
|
||||||
if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
|
|
||||||
// Make sure System Register access is enabled (SRE). This depends on the
|
|
||||||
// higher privilege level giving us permission, otherwise we will either
|
|
||||||
// cause an exception here, or the write doesn't stick in which case we need
|
|
||||||
// to fall back to the GICv2 MMIO interface.
|
|
||||||
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
|
|
||||||
// at the same exception level.
|
|
||||||
// It is the OS responsibility to set this bit.
|
|
||||||
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
|
|
||||||
if (!(IccSre & ICC_SRE_EL2_SRE)) {
|
|
||||||
ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
|
|
||||||
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
|
|
||||||
}
|
|
||||||
if (IccSre & ICC_SRE_EL2_SRE) {
|
|
||||||
return ARM_GIC_ARCH_REVISION_3;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return ARM_GIC_ARCH_REVISION_2;
|
|
||||||
}
|
|
@@ -23,7 +23,7 @@ ArmGicGetSupportedArchRevision (
|
|||||||
// feature is implemented on the CPU. This is also convenient as our GICv3
|
// feature is implemented on the CPU. This is also convenient as our GICv3
|
||||||
// driver requires SRE. If only Memory mapped access is available we try to
|
// driver requires SRE. If only Memory mapped access is available we try to
|
||||||
// drive the GIC as a v2.
|
// drive the GIC as a v2.
|
||||||
if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
|
if (ArmHasGicSystemRegisters ()) {
|
||||||
// Make sure System Register access is enabled (SRE). This depends on the
|
// Make sure System Register access is enabled (SRE). This depends on the
|
||||||
// higher privilege level giving us permission, otherwise we will either
|
// higher privilege level giving us permission, otherwise we will either
|
||||||
// cause an exception here, or the write doesn't stick in which case we need
|
// cause an exception here, or the write doesn't stick in which case we need
|
@@ -13,11 +13,8 @@
|
|||||||
VERSION_STRING = 1.0
|
VERSION_STRING = 1.0
|
||||||
LIBRARY_CLASS = ArmGicArchLib|SEC
|
LIBRARY_CLASS = ArmGicArchLib|SEC
|
||||||
|
|
||||||
[Sources.ARM]
|
[Sources]
|
||||||
Arm/ArmGicArchLib.c
|
ArmGicArchLib.c
|
||||||
|
|
||||||
[Sources.AARCH64]
|
|
||||||
AArch64/ArmGicArchLib.c
|
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
MdePkg/MdePkg.dec
|
MdePkg/MdePkg.dec
|
||||||
|
@@ -2,6 +2,7 @@
|
|||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
|
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
@@ -71,3 +72,35 @@ ArmCleanDataCache (
|
|||||||
ArmDataSynchronizationBarrier ();
|
ArmDataSynchronizationBarrier ();
|
||||||
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Check whether the CPU supports the GIC system register interface (any version)
|
||||||
|
|
||||||
|
@return Whether GIC System Register Interface is supported
|
||||||
|
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
ArmHasGicSystemRegisters (
|
||||||
|
VOID
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) != 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Checks if CCIDX is implemented.
|
||||||
|
|
||||||
|
@retval TRUE CCIDX is implemented.
|
||||||
|
@retval FALSE CCIDX is not implemented.
|
||||||
|
**/
|
||||||
|
BOOLEAN
|
||||||
|
EFIAPI
|
||||||
|
ArmHasCcidx (
|
||||||
|
VOID
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINTN Mmfr2;
|
||||||
|
|
||||||
|
Mmfr2 = ArmReadIdAA64Mmfr2 ();
|
||||||
|
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
|
||||||
|
}
|
||||||
|
@@ -2,13 +2,14 @@
|
|||||||
|
|
||||||
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
|
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
|
||||||
|
Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
|
||||||
|
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
|
||||||
**/
|
**/
|
||||||
|
|
||||||
#ifndef __AARCH64_LIB_H__
|
#ifndef AARCH64_LIB_H_
|
||||||
#define __AARCH64_LIB_H__
|
#define AARCH64_LIB_H_
|
||||||
|
|
||||||
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
|
typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
|
||||||
|
|
||||||
@@ -35,5 +36,21 @@ ArmCleanInvalidateDataCacheEntryBySetWay (
|
|||||||
IN UINTN SetWayFormat
|
IN UINTN SetWayFormat
|
||||||
);
|
);
|
||||||
|
|
||||||
#endif // __AARCH64_LIB_H__
|
UINTN
|
||||||
|
EFIAPI
|
||||||
|
ArmReadIdAA64Pfr0 (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
/** Reads the ID_AA64MMFR2_EL1 register.
|
||||||
|
|
||||||
|
@return The contents of the ID_AA64MMFR2_EL1 register.
|
||||||
|
**/
|
||||||
|
UINTN
|
||||||
|
EFIAPI
|
||||||
|
ArmReadIdAA64Mmfr2 (
|
||||||
|
VOID
|
||||||
|
);
|
||||||
|
|
||||||
|
#endif // AARCH64_LIB_H_
|
||||||
|
|
||||||
|
@@ -3,6 +3,7 @@
|
|||||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
|
||||||
# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
|
# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.
|
||||||
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
# Copyright (c) 2016, Linaro Limited. All rights reserved.
|
||||||
|
# Copyright (c) 2020, NUVIA Inc. All rights reserved.
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
#
|
#
|
||||||
@@ -395,7 +396,7 @@ ASM_FUNC(ArmReadVBar)
|
|||||||
ASM_FUNC(ArmEnableVFP)
|
ASM_FUNC(ArmEnableVFP)
|
||||||
// Check whether floating-point is implemented in the processor.
|
// Check whether floating-point is implemented in the processor.
|
||||||
mov x1, x30 // Save LR
|
mov x1, x30 // Save LR
|
||||||
bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)
|
bl ArmReadIdAA64Pfr0 // Read EL1 Processor Feature Register (PFR0)
|
||||||
mov x30, x1 // Restore LR
|
mov x30, x1 // Restore LR
|
||||||
ubfx x0, x0, #16, #4 // Extract the FP bits 16:19
|
ubfx x0, x0, #16, #4 // Extract the FP bits 16:19
|
||||||
cmp x0, #0xF // Check if FP bits are '1111b',
|
cmp x0, #0xF // Check if FP bits are '1111b',
|
||||||
@@ -424,6 +425,9 @@ ASM_FUNC(ArmCallWFI)
|
|||||||
wfi
|
wfi
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
ASM_FUNC(ArmReadIdAA64Mmfr2)
|
||||||
|
mrs x0, ID_AA64MMFR2_EL1 // read EL1 MMFR2
|
||||||
|
ret
|
||||||
|
|
||||||
ASM_FUNC(ArmReadMpidr)
|
ASM_FUNC(ArmReadMpidr)
|
||||||
mrs x0, mpidr_el1 // read EL1 MPIDR
|
mrs x0, mpidr_el1 // read EL1 MPIDR
|
||||||
@@ -448,19 +452,11 @@ ASM_FUNC(ArmIsArchTimerImplemented)
|
|||||||
ret
|
ret
|
||||||
|
|
||||||
|
|
||||||
ASM_FUNC(ArmReadIdPfr0)
|
ASM_FUNC(ArmReadIdAA64Pfr0)
|
||||||
mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
|
mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
|
||||||
// Q: id_aa64pfr1_el1 not defined yet. What does this function want to access?
|
|
||||||
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
|
|
||||||
// See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
|
|
||||||
// Not defined yet, but stick in here for now, should read all zeros.
|
|
||||||
ASM_FUNC(ArmReadIdPfr1)
|
|
||||||
mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register
|
|
||||||
ret
|
|
||||||
|
|
||||||
// VOID ArmWriteHcr(UINTN Hcr)
|
// VOID ArmWriteHcr(UINTN Hcr)
|
||||||
ASM_FUNC(ArmWriteHcr)
|
ASM_FUNC(ArmWriteHcr)
|
||||||
msr hcr_el2, x0 // Write the passed HCR value
|
msr hcr_el2, x0 // Write the passed HCR value
|
||||||
|
@@ -84,7 +84,7 @@ ASM_FUNC(ArmDisableAllExceptions)
|
|||||||
ret
|
ret
|
||||||
|
|
||||||
|
|
||||||
// UINT32
|
// UINTN
|
||||||
// ReadCCSIDR (
|
// ReadCCSIDR (
|
||||||
// IN UINT32 CSSELR
|
// IN UINT32 CSSELR
|
||||||
// )
|
// )
|
||||||
|
@@ -60,7 +60,11 @@ ASM_FUNC(ArmDisableInterrupts)
|
|||||||
isb
|
isb
|
||||||
bx LR
|
bx LR
|
||||||
|
|
||||||
// UINT32
|
ASM_FUNC(ArmReadIdMmfr4)
|
||||||
|
mrc p15,0,r0,c0,c2,6 @ Read ID_MMFR4 Register
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
// UINTN
|
||||||
// ReadCCSIDR (
|
// ReadCCSIDR (
|
||||||
// IN UINT32 CSSELR
|
// IN UINT32 CSSELR
|
||||||
// )
|
// )
|
||||||
@@ -70,6 +74,16 @@ ASM_FUNC(ReadCCSIDR)
|
|||||||
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
|
||||||
bx lr
|
bx lr
|
||||||
|
|
||||||
|
// UINT32
|
||||||
|
// ReadCCSIDR2 (
|
||||||
|
// IN UINT32 CSSELR
|
||||||
|
// )
|
||||||
|
ASM_FUNC(ReadCCSIDR2)
|
||||||
|
mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
|
||||||
|
isb
|
||||||
|
mrc p15,1,r0,c0,c0,2 @ Read current CP15 Cache Size ID Register (CCSIDR2)
|
||||||
|
bx lr
|
||||||
|
|
||||||
// UINT32
|
// UINT32
|
||||||
// ReadCLIDR (
|
// ReadCLIDR (
|
||||||
// IN UINT32 CSSELR
|
// IN UINT32 CSSELR
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user