ff3c97807a
Derive the size of the GCD memory space map directly from the CPU's information registers rather than from the PcdPrePiCpuMemorySize PCD, which will be removed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
137 lines
4.3 KiB
C
Executable File
137 lines
4.3 KiB
C
Executable File
/** @file
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*
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <PiPei.h>
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#include <Pi/PiBootMode.h>
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#include <Library/PrePiLib.h>
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#include <Library/PrintLib.h>
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#include <Library/PrePiHobListPointerLib.h>
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#include <Library/TimerLib.h>
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#include <Library/PerformanceLib.h>
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#include <Library/CacheMaintenanceLib.h>
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#include <Ppi/GuidedSectionExtraction.h>
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#include <Ppi/ArmMpCoreInfo.h>
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#include "PrePi.h"
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VOID
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EFIAPI
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ProcessLibraryConstructorList (
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VOID
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);
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VOID
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PrePiMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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)
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{
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EFI_HOB_HANDOFF_INFO_TABLE* HobList;
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EFI_STATUS Status;
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CHAR8 Buffer[100];
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UINTN CharCount;
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UINTN StacksSize;
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// Initialize the architecture specific bits
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ArchInitialize ();
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// Declare the PI/UEFI memory region
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HobList = HobConstructor (
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(VOID*)UefiMemoryBase,
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FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),
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(VOID*)UefiMemoryBase,
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(VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks
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);
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PrePeiSetHobList (HobList);
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//
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// Ensure that the loaded image is invalidated in the caches, so that any
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// modifications we made with the caches and MMU off (such as the applied
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// relocations) don't become invisible once we turn them on.
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//
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InvalidateDataCacheRange((VOID *)(UINTN)PcdGet64 (PcdFdBaseAddress), PcdGet32 (PcdFdSize));
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// Initialize MMU and Memory HOBs (Resource Descriptor HOBs)
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Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
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ASSERT_EFI_ERROR (Status);
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// Initialize the Serial Port
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SerialPortInitialize ();
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CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",
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(CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
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SerialPortWrite ((UINT8 *) Buffer, CharCount);
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// Create the Stacks HOB (reserve the memory for all stacks)
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
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BuildStackHob (StacksBase, StacksSize);
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//TODO: Call CpuPei as a library
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BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
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// Set the Boot Mode
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SetBootMode (BOOT_WITH_FULL_CONFIGURATION);
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// Initialize Platform HOBs (CpuHob and FvHob)
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Status = PlatformPeim ();
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ASSERT_EFI_ERROR (Status);
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// Now, the HOB List has been initialized, we can register performance information
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PERF_START (NULL, "PEI", NULL, StartTimeStamp);
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// SEC phase needs to run library constructors by hand.
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ProcessLibraryConstructorList ();
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// Assume the FV that contains the SEC (our code) also contains a compressed FV.
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Status = DecompressFirstFv ();
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ASSERT_EFI_ERROR (Status);
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// Load the DXE Core and transfer control to it
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Status = LoadDxeCoreFromFv (NULL, 0);
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ASSERT_EFI_ERROR (Status);
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}
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VOID
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CEntryPoint (
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IN UINTN MpId,
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase
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)
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{
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UINT64 StartTimeStamp;
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if (PerformanceMeasurementEnabled ()) {
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// Initialize the Timer Library to setup the Timer HW controller
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TimerConstructor ();
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// We cannot call yet the PerformanceLib because the HOB List has not been initialized
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StartTimeStamp = GetPerformanceCounter ();
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} else {
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StartTimeStamp = 0;
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}
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// Data Cache enabled on Primary core when MMU is enabled.
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ArmDisableDataCache ();
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// Invalidate instruction cache
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ArmInvalidateInstructionCache ();
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// Enable Instruction Caches on all cores.
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ArmEnableInstructionCache ();
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PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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// DXE Core should always load and never return
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ASSERT (FALSE);
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}
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