d20ae95a13
This is for conformance with the TCG "Platform Reset Attack Mitigation Specification". Because clearing the CPU caches at boot doesn't impact performance significantly, do it unconditionally, for simplicity's sake. Flush the cache on all logical processors, thanks to EFI_PEI_MP_SERVICES_PPI and CacheMaintenanceLib. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Anthony Perard <anthony.perard@citrix.com> Cc: Julien Grall <julien.grall@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Tested-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> [lersek@redhat.com: remove bogus Message-Id line from commit msg]
124 lines
2.1 KiB
C
124 lines
2.1 KiB
C
/** @file
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Platform PEI module include file.
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PLATFORM_PEI_H_INCLUDED_
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#define _PLATFORM_PEI_H_INCLUDED_
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#include <IndustryStandard/E820.h>
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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);
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VOID
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AddressWidthInitialization (
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VOID
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);
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VOID
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Q35TsegMbytesInitialization (
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VOID
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);
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EFI_STATUS
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PublishPeiMemory (
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VOID
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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);
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VOID
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InitializeRamRegions (
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VOID
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);
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EFI_STATUS
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PeiFvInitialization (
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VOID
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);
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VOID
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InstallFeatureControlCallback (
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VOID
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);
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VOID
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InstallClearCacheCallback (
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VOID
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);
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EFI_STATUS
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InitializeXen (
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VOID
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);
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BOOLEAN
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XenDetect (
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VOID
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);
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VOID
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AmdSevInitialize (
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VOID
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);
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extern BOOLEAN mXen;
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VOID
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XenPublishRamRegions (
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VOID
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);
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extern EFI_BOOT_MODE mBootMode;
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extern BOOLEAN mS3Supported;
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extern UINT8 mPhysMemAddressWidth;
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extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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