0df5056012
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093 Return Stack Buffer (RSB) is used to predict the target of RET instructions. When the RSB underflows, some processors may fall back to using branch predictors. This might impact software using the retpoline mitigation strategy on those processors. This commit will add RSB stuffing logic before returning from SMM (the RSM instruction) to avoid interfering with non-SMM usage of the retpoline technique. After the stuffing, RSB entries will contain a trap like: @SpecTrap: pause lfence jmp @SpecTrap A more detailed explanation of the purpose of commit is under the 'Branch target injection mitigation' section of the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Please note that this commit requires further actions (BZ 1091) to remove the duplicated 'StuffRsb.inc' files and merge them into one under a UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
283 lines
8.0 KiB
NASM
283 lines
8.0 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiEntry.nasm
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;
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; Abstract:
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;
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; Code template of the SMI handler for a particular processor
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsb.inc"
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%define MSR_IA32_MISC_ENABLE 0x1A0
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%define MSR_EFER 0xc0000080
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%define MSR_EFER_XD 0x800
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;
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; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
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;
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%define DSC_OFFSET 0xfb00
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%define DSC_GDTPTR 0x48
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%define DSC_GDTSIZ 0x50
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%define DSC_CS 0x14
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%define DSC_DS 0x16
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%define DSC_SS 0x18
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%define DSC_OTHERSEG 0x1a
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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%define TSS_SEGMENT 0x40
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extern ASM_PFX(SmiRendezvous)
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extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
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extern ASM_PFX(CpuSmmDebugEntry)
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extern ASM_PFX(CpuSmmDebugExit)
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global ASM_PFX(gcStmSmiHandlerTemplate)
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global ASM_PFX(gcStmSmiHandlerSize)
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global ASM_PFX(gcStmSmiHandlerOffset)
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global ASM_PFX(gStmSmiCr3)
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global ASM_PFX(gStmSmiStack)
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global ASM_PFX(gStmSmbase)
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global ASM_PFX(gStmXdSupported)
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extern ASM_PFX(gStmSmiHandlerIdtr)
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ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
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ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
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ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
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ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1
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SECTION .text
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BITS 16
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ASM_PFX(gcStmSmiHandlerTemplate):
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_StmSmiEntryPoint:
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mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
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mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
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dec ax
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mov [cs:bx], ax
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mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
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mov [cs:bx + 2], eax
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mov ebp, eax ; ebp = GDT base
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o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
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mov ax, PROTECT_MODE_CS
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mov [cs:bx-0x2],ax
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o32 mov edi, strict dword 0
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StmSmbasePatch:
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lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]
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mov [cs:bx-0x6],eax
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mov ebx, cr0
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and ebx, 0x9ffafff3
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or ebx, 0x23
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mov cr0, ebx
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jmp dword 0x0:0x0
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_StmGdtDesc:
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DW 0
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DD 0
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BITS 32
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@32bit:
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mov ax, PROTECT_MODE_DS
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o16 mov ds, ax
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o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax
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mov esp, strict dword 0
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StmSmiStackPatch:
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mov eax, ASM_PFX(gStmSmiHandlerIdtr)
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lidt [eax]
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jmp ProtFlatMode
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ProtFlatMode:
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mov eax, strict dword 0
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StmSmiCr3Patch:
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mov cr3, eax
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;
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; Need to test for CR4 specific bit support
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;
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mov eax, 1
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cpuid ; use CPUID to determine if specific CR4 bits are supported
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xor eax, eax ; Clear EAX
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test edx, BIT2 ; Check for DE capabilities
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jz .0
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or eax, BIT3
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.0:
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test edx, BIT6 ; Check for PAE capabilities
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jz .1
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or eax, BIT5
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.1:
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test edx, BIT7 ; Check for MCE capabilities
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jz .2
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or eax, BIT6
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.2:
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test edx, BIT24 ; Check for FXSR capabilities
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jz .3
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or eax, BIT9
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.3:
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test edx, BIT25 ; Check for SSE capabilities
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jz .4
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or eax, BIT10
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.4: ; as cr4.PGE is not set here, refresh cr3
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mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
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cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
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jz .6
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; Load TSS
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mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
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mov eax, TSS_SEGMENT
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ltr ax
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.6:
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; enable NXE if supported
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mov al, strict byte 1
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StmXdSupportedPatch:
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cmp al, 0
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jz @SkipXd
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;
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; Check XD disable bit
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;
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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push edx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .5
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.5:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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jmp @XdDone
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@SkipXd:
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sub esp, 4
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@XdDone:
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mov ebx, cr0
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or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
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mov cr0, ebx
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lea ebx, [edi + DSC_OFFSET]
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mov ax, [ebx + DSC_DS]
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mov ds, eax
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mov ax, [ebx + DSC_OTHERSEG]
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mov es, eax
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mov fs, eax
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mov gs, eax
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mov ax, [ebx + DSC_SS]
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mov ss, eax
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CommonHandler:
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mov ebx, [esp + 4] ; CPU Index
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push ebx
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mov eax, ASM_PFX(CpuSmmDebugEntry)
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call eax
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add esp, 4
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push ebx
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mov eax, ASM_PFX(SmiRendezvous)
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call eax
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add esp, 4
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push ebx
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mov eax, ASM_PFX(CpuSmmDebugExit)
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call eax
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add esp, 4
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz .7
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pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .7
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.7:
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StuffRsb32
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rsm
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_StmSmiHandler:
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;
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; Check XD disable bit
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;
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xor esi, esi
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz @StmXdDone
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .5
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.5:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone:
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push esi
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; below step is needed, because STM does not run above code.
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; we have to run below code to set IDT/CR0/CR4
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mov eax, ASM_PFX(gStmSmiHandlerIdtr)
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lidt [eax]
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mov eax, cr0
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or eax, 0x80010023 ; enable paging + WP + NE + MP + PE
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mov cr0, eax
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;
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; Need to test for CR4 specific bit support
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;
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mov eax, 1
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cpuid ; use CPUID to determine if specific CR4 bits are supported
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mov eax, cr4 ; init EAX
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test edx, BIT2 ; Check for DE capabilities
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jz .0
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or eax, BIT3
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.0:
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test edx, BIT6 ; Check for PAE capabilities
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jz .1
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or eax, BIT5
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.1:
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test edx, BIT7 ; Check for MCE capabilities
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jz .2
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or eax, BIT6
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.2:
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test edx, BIT24 ; Check for FXSR capabilities
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jz .3
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or eax, BIT9
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.3:
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test edx, BIT25 ; Check for SSE capabilities
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jz .4
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or eax, BIT10
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.4: ; as cr4.PGE is not set here, refresh cr3
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mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
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; STM init finish
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jmp CommonHandler
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ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
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ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
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global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)
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ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):
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ret
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