02f7fd158e
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093 Return Stack Buffer (RSB) is used to predict the target of RET instructions. When the RSB underflows, some processors may fall back to using branch predictors. This might impact software using the retpoline mitigation strategy on those processors. This commit will add RSB stuffing logic before returning from SMM (the RSM instruction) to avoid interfering with non-SMM usage of the retpoline technique. After the stuffing, RSB entries will contain a trap like: @SpecTrap: pause lfence jmp @SpecTrap A more detailed explanation of the purpose of commit is under the 'Branch target injection mitigation' section of the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Please note that this commit requires further actions (BZ 1091) to remove the duplicated 'StuffRsb.inc' files and merge them into one under a UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
103 lines
3.1 KiB
NASM
103 lines
3.1 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmmInit.nasm
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;
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; Abstract:
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;
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; Functions for relocating SMBASE's for all processors
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;
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;-------------------------------------------------------------------------------
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%include "StuffRsb.inc"
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extern ASM_PFX(SmmInitHandler)
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extern ASM_PFX(mRebasedFlag)
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extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gPatchSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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%define PROTECT_MODE_CS 0x8
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%define PROTECT_MODE_DS 0x20
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SECTION .text
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ASM_PFX(gcSmiInitGdtr):
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DW 0
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DQ 0
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global ASM_PFX(SmmStartup)
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BITS 16
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ASM_PFX(SmmStartup):
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mov eax, 0x80000001 ; read capability
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cpuid
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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and ebx, BIT20 ; extract NX capability bit
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shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr3):
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mov cr3, eax
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o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr4):
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mov cr4, eax
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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or eax, ebx ; set NXE bit if NX is available
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wrmsr
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr0):
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mov di, PROTECT_MODE_DS
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mov cr0, eax
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jmp PROTECT_MODE_CS : dword @32bit
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BITS 32
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@32bit:
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mov ds, edi
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mov es, edi
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mov fs, edi
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mov gs, edi
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mov ss, edi
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mov esp, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmInitStack):
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call ASM_PFX(SmmInitHandler)
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StuffRsb32
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rsm
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BITS 16
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ASM_PFX(gcSmmInitTemplate):
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mov ebp, ASM_PFX(SmmStartup)
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sub ebp, 0x30000
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jmp ebp
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ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
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BITS 32
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global ASM_PFX(SmmRelocationSemaphoreComplete)
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ASM_PFX(SmmRelocationSemaphoreComplete):
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push eax
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mov eax, [ASM_PFX(mRebasedFlag)]
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mov byte [eax], 1
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pop eax
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jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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ret
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