04ff9d663b
In Intel datasheet 316966-002 (the "q35 spec"), Table 5-1 "DRAM Controller Register Address Map (D0:F0)" leaves the byte register at config space offset 0x9C unused. On QEMU's Q35 board, for detecting the "SMRAM at default SMBASE" feature, firmware is expected to write MCH_DEFAULT_SMBASE_QUERY (0xFF) to offset MCH_DEFAULT_SMBASE_CTL (0x9C), and read back the register. If the value is MCH_DEFAULT_SMBASE_IN_RAM (0x01), then the feature is available, and the range mentioned below is open (accessible to code running outside of SMM). Then, once firmware writes MCH_DEFAULT_SMBASE_LCK (0x02) to the register, the MCH_DEFAULT_SMBASE_SIZE (128KB) range at 0x3_0000 (SMM_DEFAULT_SMBASE) gets closed and locked down, and the register becomes read-only. The area is reopened, and the register becomes read/write, at platform reset. Add the above-listed macros to "Q35MchIch9.h". (There are some other unused offsets in Table 5-1; for example we had scavenged 0x50 for implementing the extended TSEG feature. 0x9C is the first byte-wide register standing in isolation after 0x50.) Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Message-Id: <20200129214412.2361-4-lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
127 lines
3.5 KiB
C
127 lines
3.5 KiB
C
/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 316966-002
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- Intel(R) datasheet 316972-004
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __Q35_MCH_ICH9_H__
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#define __Q35_MCH_ICH9_H__
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#include <Library/PciLib.h>
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#include <Uefi/UefiBaseType.h>
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#include <Uefi/UefiSpec.h>
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#include <Protocol/PciRootBridgeIo.h>
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//
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// Host Bridge Device ID (DID) value for Q35/MCH
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//
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#define INTEL_Q35_MCH_DEVICE_ID 0x29C0
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define MCH_EXT_TSEG_MB 0x50
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#define MCH_EXT_TSEG_MB_QUERY 0xFFFF
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#define MCH_GGC 0x52
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#define MCH_GGC_IVD BIT1
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#define MCH_PCIEXBAR_LOW 0x60
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#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF
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#define MCH_PCIEXBAR_BUS_FF 0
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#define MCH_PCIEXBAR_EN BIT0
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#define MCH_PCIEXBAR_HIGH 0x64
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#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0
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#define MCH_PAM0 0x90
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#define MCH_PAM1 0x91
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#define MCH_PAM2 0x92
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#define MCH_PAM3 0x93
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#define MCH_PAM4 0x94
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#define MCH_PAM5 0x95
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#define MCH_PAM6 0x96
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#define MCH_DEFAULT_SMBASE_CTL 0x9C
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#define MCH_DEFAULT_SMBASE_QUERY 0xFF
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#define MCH_DEFAULT_SMBASE_IN_RAM 0x01
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#define MCH_DEFAULT_SMBASE_LCK 0x02
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#define MCH_DEFAULT_SMBASE_SIZE SIZE_128KB
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#define MCH_SMRAM 0x9D
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#define MCH_SMRAM_D_LCK BIT4
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#define MCH_SMRAM_G_SMRAME BIT3
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#define MCH_ESMRAMC 0x9E
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#define MCH_ESMRAMC_H_SMRAME BIT7
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#define MCH_ESMRAMC_E_SMERR BIT6
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#define MCH_ESMRAMC_SM_CACHE BIT5
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#define MCH_ESMRAMC_SM_L1 BIT4
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#define MCH_ESMRAMC_SM_L2 BIT3
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#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1)
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#define MCH_ESMRAMC_TSEG_8MB BIT2
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#define MCH_ESMRAMC_TSEG_2MB BIT1
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#define MCH_ESMRAMC_TSEG_1MB 0
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#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
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#define MCH_ESMRAMC_T_EN BIT0
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#define MCH_GBSM 0xA4
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#define MCH_GBSM_MB_SHIFT 20
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#define MCH_BGSM 0xA8
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#define MCH_BGSM_MB_SHIFT 20
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#define MCH_TSEGMB 0xAC
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#define MCH_TSEGMB_MB_SHIFT 20
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#define MCH_TOLUD 0xB0
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#define MCH_TOLUD_MB_SHIFT 4
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//
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// B/D/F/Type: 0/0x1f/0/PCI
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//
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#define POWER_MGMT_REGISTER_Q35(Offset) \
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PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset))
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#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \
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EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset))
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#define ICH9_PMBASE 0x40
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#define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7)
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#define ICH9_ACPI_CNTL 0x44
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#define ICH9_ACPI_CNTL_ACPI_EN BIT7
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#define ICH9_GEN_PMCON_1 0xA0
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#define ICH9_GEN_PMCON_1_SMI_LOCK BIT4
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#define ICH9_RCBA 0xF0
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#define ICH9_RCBA_EN BIT0
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//
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// IO ports
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//
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#define ICH9_APM_CNT 0xB2
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#define ICH9_APM_STS 0xB3
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#define ICH9_CPU_HOTPLUG_BASE 0x0CD8
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//
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// IO ports relative to PMBASE
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//
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#define ICH9_PMBASE_OFS_SMI_EN 0x30
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#define ICH9_SMI_EN_APMC_EN BIT5
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#define ICH9_SMI_EN_GBL_SMI_EN BIT0
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#define ICH9_ROOT_COMPLEX_BASE 0xFED1C000
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#endif
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