bbc04972bc
In coreboot, we mark GPU prefmem above 4GB, because NVIDIA wants a lot
(16GB region on the 30 series), otherwise coreboot will obviously fail
to allocate the resources.
In EDK2, we then end up hitting this assert:
InitRootBridge: populated root bus 0, with room for 36 subordinate bus(es)
RootBridge: PciRoot(0x0)
Support/Attr: 7001F / 7001F
DmaAbove4G: No
NoExtConfSpace: No
AllocAttr: 0 ()
Bus: 0 - 24 Translation=0
Io: 1000 - EFFF Translation=0
Mem: 80400000 - 1001FFFFFF Translation=0
MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
PMem: FFFFFFFFFFFFFFFF - 0 Translation=0
PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0
ASSERT [PciHostBridgeDxe] .../edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c(120): Bridge->Mem.Limit < 0x0000000100000000ULL
So, bring back Pci*NoEnumerationDxe from the deleted DuetPkg, which
doesn't check anything and let's us boot.
Signed-off-by: Tim Crawford <tcrawford@system76.com>
67 lines
1.7 KiB
INI
67 lines
1.7 KiB
INI
## @file
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#
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# Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# Abstract:
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = PcatPciRootBridge
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FILE_GUID = 0F7EC77A-1EE1-400f-A99D-7CBD1FEB181E
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = InitializePcatPciRootBridge
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[Packages]
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MdePkg/MdePkg.dec
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UefiPayloadPkg/UefiPayloadPkg.dec
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[LibraryClasses]
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UefiDriverEntryPoint
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UefiLib
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MemoryAllocationLib
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UefiBootServicesTableLib
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DebugLib
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BaseMemoryLib
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DevicePathLib
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HobLib
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[Sources]
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PcatPciRootBridge.h
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PcatPciRootBridge.c
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PcatPciRootBridgeDevicePath.c
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PcatPciRootBridgeIo.c
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DeviceIo.h
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DeviceIo.c
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[Sources.ia32]
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Ia32/PcatIo.c
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[Sources.x64]
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X64/PcatIo.c
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[Protocols]
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gEfiPciRootBridgeIoProtocolGuid
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gEfiDeviceIoProtocolGuid
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gEfiCpuIo2ProtocolGuid
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[Guids]
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gEfiPciOptionRomTableGuid
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gEfiPciExpressBaseAddressGuid
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[Depex]
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gEfiCpuIo2ProtocolGuid
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