0095070e70
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
108 lines
2.5 KiB
C
108 lines
2.5 KiB
C
/** @file
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MSR Definitions.
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Provides defines for Machine Specific Registers(MSR) indexes. Data structures
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are provided for MSRs that contain one or more bit fields. If the MSR value
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returned is a single 32-bit or 64-bit value, then a data structure is not
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provided for that MSR.
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Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Specification Reference:
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AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
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**/
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#ifndef __FAM17_MSR_H__
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#define __FAM17_MSR_H__
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/**
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Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
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**/
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#define MSR_SEV_ES_GHCB 0xc0010130
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/**
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MSR information returned for #MSR_SEV_ES_GHCB
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**/
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typedef union {
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struct {
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UINT32 Function:12;
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UINT32 Reserved1:20;
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UINT32 Reserved2:32;
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} GhcbInfo;
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struct {
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UINT8 Reserved[3];
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UINT8 SevEncryptionBitPos;
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UINT16 SevEsProtocolMin;
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UINT16 SevEsProtocolMax;
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} GhcbProtocol;
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struct {
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UINT32 Function:12;
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UINT32 ReasonCodeSet:4;
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UINT32 ReasonCode:8;
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UINT32 Reserved1:8;
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UINT32 Reserved2:32;
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} GhcbTerminate;
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VOID *Ghcb;
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UINT64 GhcbPhysicalAddress;
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} MSR_SEV_ES_GHCB_REGISTER;
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#define GHCB_INFO_SEV_INFO 1
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#define GHCB_INFO_SEV_INFO_GET 2
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#define GHCB_INFO_CPUID_REQUEST 4
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#define GHCB_INFO_CPUID_RESPONSE 5
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#define GHCB_INFO_TERMINATE_REQUEST 256
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#define GHCB_TERMINATE_GHCB 0
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#define GHCB_TERMINATE_GHCB_GENERAL 0
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#define GHCB_TERMINATE_GHCB_PROTOCOL 1
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/**
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Secure Encrypted Virtualization (SEV) status register
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**/
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#define MSR_SEV_STATUS 0xc0010131
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/**
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MSR information returned for #MSR_SEV_STATUS
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
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///
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UINT32 SevBit:1;
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///
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/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
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///
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UINT32 SevEsBit:1;
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///
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/// [Bit 2] Secure Nested Paging (SevSnp) is enabled
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///
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UINT32 SevSnpBit:1;
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UINT32 Reserved2:29;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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///
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/// All bit fields as a 64-bit value
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///
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UINT64 Uint64;
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} MSR_SEV_STATUS_REGISTER;
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#endif
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