00aa71ce20
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
77 lines
1.7 KiB
NASM
77 lines
1.7 KiB
NASM
;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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SECTION .text
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%include "PushPopRegsNasm.inc"
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STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose register * rax index
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;
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; Following functions will be provided in C
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;
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extern ASM_PFX(Loader2PeiSwitchStack)
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extern ASM_PFX(FspApiCallingCheck)
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;
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; Following functions will be provided in ASM
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;
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extern ASM_PFX(FspApiCommonContinue)
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extern ASM_PFX(AsmGetFspInfoHeader)
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;----------------------------------------------------------------------------
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; FspApiCommon API
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;
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; This is the FSP API common entry point to resume the FSP execution
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspApiCommon)
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ASM_PFX(FspApiCommon):
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;
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; RAX holds the API index
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;
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;
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; Stack must be ready
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;
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push rax
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add rsp, 8
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cmp rax, [rsp - 8]
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jz FspApiCommon1
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mov rax, 08000000000000003h
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jmp exit
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FspApiCommon1:
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;
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; Verify the calling condition
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;
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PUSHA_64
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mov rdx, rcx ; move ApiParam to rdx
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mov rcx, rax ; move ApiIdx to rcx
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call ASM_PFX(FspApiCallingCheck)
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cmp rax, 0
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jz FspApiCommon2
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mov [rsp + STACK_SAVED_RAX_OFFSET], rax
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POPA_64
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exit:
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ret
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FspApiCommon2:
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POPA_64
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cmp rax, 3 ; FspMemoryInit API
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jz FspApiCommon3
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cmp rax, 6 ; FspMultiPhaseSiInitApiIndex API
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jz FspApiCommon3
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call ASM_PFX(AsmGetFspInfoHeader)
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jmp ASM_PFX(Loader2PeiSwitchStack)
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FspApiCommon3:
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jmp ASM_PFX(FspApiCommonContinue)
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