00aa71ce20
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
59 lines
1.2 KiB
INI
59 lines
1.2 KiB
INI
## @file
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# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.
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#
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# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = Fsp22SecCoreS
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FILE_GUID = DF0FCD70-264A-40BF-BBD4-06C76DB19CB1
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64
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#
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[Sources]
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SecFspApiChk.c
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SecFsp.h
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[Sources.IA32]
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Ia32/Stack.nasm
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Ia32/Fsp22ApiEntryS.nasm
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Ia32/FspApiEntryCommon.nasm
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Ia32/FspHelper.nasm
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[Sources.X64]
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X64/Stack.nasm
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X64/Fsp22ApiEntryS.nasm
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X64/FspApiEntryCommon.nasm
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X64/FspHelper.nasm
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[Binaries.Ia32]
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RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
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[Packages]
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MdePkg/MdePkg.dec
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IntelFsp2Pkg/IntelFsp2Pkg.dec
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[LibraryClasses]
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BaseMemoryLib
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DebugLib
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BaseLib
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PciCf8Lib
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SerialPortLib
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FspSwitchStackLib
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FspCommonLib
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FspSecPlatformLib
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[Ppis]
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gEfiTemporaryRamSupportPpiGuid ## PRODUCES
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