ec25e904c7
On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol
Speed ID Value) indices are shared between Protocol Speed ID DWORD' in
the extended capabilities registers for both USB2 (Full Speed) and USB3
(Super Speed).
An example can be found below:
XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps
XhciPsivGetPsid: found 3 PSID entries
XhciPsivGetPsid: looking for port speed 1
XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12
XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500
XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480
XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps
XhciPsivGetPsid: found 3 PSID entries
XhciPsivGetPsid: looking for port speed 1
XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5
XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10
XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248
The result is edk2 detecting USB2 devices as USB3 devices, which
consequently causes enumeration to fail.
To avoid incorrect detection, check the Compatible Port Offset to find
the starting Port of Root Hubs that support the protocol.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
947 lines
24 KiB
C
947 lines
24 KiB
C
/** @file
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The XHCI register operation routines.
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Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Xhci.h"
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/**
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Read 1-byte width XHCI capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 1-byte width capability register.
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@return The register content read.
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@retval If err, return 0xFF.
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**/
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UINT8
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XhcReadCapReg8 (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT8 Data;
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EFI_STATUS Status;
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint8,
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XHC_BAR_INDEX,
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(UINT64)Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
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Data = 0xFF;
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}
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return Data;
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}
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/**
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Read 4-bytes width XHCI capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width capability register.
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@return The register content read.
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@retval If err, return 0xFFFFFFFF.
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**/
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UINT32
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XhcReadCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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(UINT64)Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Read 4-bytes width XHCI Operational register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width operational register.
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@return The register content read.
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@retval If err, return 0xFFFFFFFF.
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**/
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UINT32
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XhcReadOpReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->CapLength != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->CapLength + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the 4-bytes width XHCI operational register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the 4-bytes width operational register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteOpReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->CapLength != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->CapLength + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Write the data to the XHCI door bell register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the door bell register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteDoorBellReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->DBOff != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->DBOff + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Read XHCI runtime register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@return The register content read
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**/
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UINT32
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XhcReadRuntimeReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->RTSOff != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->RTSOff + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the XHCI runtime register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteRuntimeReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->RTSOff != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->RTSOff + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Read XHCI extended capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the extended capability register.
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@return The register content read
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**/
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UINT32
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XhcReadExtCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset
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)
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{
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UINT32 Data;
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EFI_STATUS Status;
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ASSERT (Xhc->ExtCapRegBase != 0);
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Status = Xhc->PciIo->Mem.Read (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->ExtCapRegBase + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));
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Data = 0xFFFFFFFF;
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}
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return Data;
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}
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/**
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Write the data to the XHCI extended capability register.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the extended capability register.
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@param Data The data to write.
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**/
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VOID
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XhcWriteExtCapReg (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Data
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)
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{
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EFI_STATUS Status;
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ASSERT (Xhc->ExtCapRegBase != 0);
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Status = Xhc->PciIo->Mem.Write (
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Xhc->PciIo,
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EfiPciIoWidthUint32,
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XHC_BAR_INDEX,
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Xhc->ExtCapRegBase + Offset,
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1,
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&Data
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));
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}
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}
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/**
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Set one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcSetRuntimeRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadRuntimeReg (Xhc, Offset);
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Data |= Bit;
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XhcWriteRuntimeReg (Xhc, Offset, Data);
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}
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/**
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Clear one bit of the runtime register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the runtime register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcClearRuntimeRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadRuntimeReg (Xhc, Offset);
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Data &= ~Bit;
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XhcWriteRuntimeReg (Xhc, Offset, Data);
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}
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/**
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Set one bit of the operational register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to set.
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**/
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VOID
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XhcSetOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadOpReg (Xhc, Offset);
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Data |= Bit;
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XhcWriteOpReg (Xhc, Offset, Data);
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}
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/**
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Clear one bit of the operational register while keeping other bits.
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operational register.
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@param Bit The bit mask of the register to clear.
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**/
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VOID
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XhcClearOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit
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)
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{
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UINT32 Data;
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Data = XhcReadOpReg (Xhc, Offset);
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Data &= ~Bit;
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XhcWriteOpReg (Xhc, Offset, Data);
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}
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/**
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Wait the operation register's bit as specified by Bit
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to become set (or clear).
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@param Xhc The XHCI Instance.
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@param Offset The offset of the operation register.
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@param Bit The bit of the register to wait for.
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@param WaitToSet Wait the bit to set or clear.
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@param Timeout The time to wait before abort (in millisecond, ms).
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@retval EFI_SUCCESS The bit successfully changed by host controller.
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@retval EFI_TIMEOUT The time out occurred.
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@retval EFI_OUT_OF_RESOURCES Memory for the timer event could not be allocated.
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**/
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EFI_STATUS
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XhcWaitOpRegBit (
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IN USB_XHCI_INSTANCE *Xhc,
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IN UINT32 Offset,
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IN UINT32 Bit,
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IN BOOLEAN WaitToSet,
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IN UINT32 Timeout
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)
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{
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EFI_STATUS Status;
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EFI_EVENT TimeoutEvent;
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TimeoutEvent = NULL;
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if (Timeout == 0) {
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return EFI_TIMEOUT;
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}
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Status = gBS->CreateEvent (
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EVT_TIMER,
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TPL_CALLBACK,
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NULL,
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NULL,
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&TimeoutEvent
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);
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if (EFI_ERROR (Status)) {
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goto DONE;
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}
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Status = gBS->SetTimer (
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TimeoutEvent,
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TimerRelative,
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EFI_TIMER_PERIOD_MILLISECONDS (Timeout)
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);
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if (EFI_ERROR (Status)) {
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goto DONE;
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}
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do {
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if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {
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Status = EFI_SUCCESS;
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goto DONE;
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}
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gBS->Stall (XHC_1_MICROSECOND);
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} while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));
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Status = EFI_TIMEOUT;
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DONE:
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if (TimeoutEvent != NULL) {
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gBS->CloseEvent (TimeoutEvent);
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}
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return Status;
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}
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|
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/**
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Set Bios Ownership
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@param Xhc The XHCI Instance.
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**/
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VOID
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XhcSetBiosOwnership (
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IN USB_XHCI_INSTANCE *Xhc
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)
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{
|
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UINT32 Buffer;
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|
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if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
|
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return;
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}
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DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);
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XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
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}
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|
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/**
|
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Clear Bios Ownership
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
**/
|
|
VOID
|
|
XhcClearBiosOwnership (
|
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IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
UINT32 Buffer;
|
|
|
|
if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
|
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return;
|
|
}
|
|
|
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DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
|
|
|
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
|
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Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);
|
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XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);
|
|
}
|
|
|
|
/**
|
|
Calculate the offset of the XHCI capability.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param CapId The XHCI Capability ID.
|
|
|
|
@return The offset of XHCI legacy support capability register.
|
|
|
|
**/
|
|
UINT32
|
|
XhcGetCapabilityAddr (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT8 CapId
|
|
)
|
|
{
|
|
UINT32 ExtCapOffset;
|
|
UINT8 NextExtCapReg;
|
|
UINT32 Data;
|
|
|
|
ExtCapOffset = 0;
|
|
|
|
do {
|
|
//
|
|
// Check if the extended capability register's capability id is USB Legacy Support.
|
|
//
|
|
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
|
|
if ((Data & 0xFF) == CapId) {
|
|
return ExtCapOffset;
|
|
}
|
|
|
|
//
|
|
// If not, then traverse all of the ext capability registers till finding out it.
|
|
//
|
|
NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
|
|
ExtCapOffset += (NextExtCapReg << 2);
|
|
} while (NextExtCapReg != 0);
|
|
|
|
return 0xFFFFFFFF;
|
|
}
|
|
|
|
/**
|
|
Calculate the offset of the xHCI Supported Protocol Capability.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field
|
|
|
|
@return The offset of xHCI Supported Protocol capability register.
|
|
|
|
**/
|
|
UINT32
|
|
XhcGetSupportedProtocolCapabilityAddr (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT8 MajorVersion
|
|
)
|
|
{
|
|
UINT32 ExtCapOffset;
|
|
UINT8 NextExtCapReg;
|
|
UINT32 Data;
|
|
UINT32 NameString;
|
|
XHC_SUPPORTED_PROTOCOL_DW0 UsbSupportDw0;
|
|
|
|
if (Xhc == NULL) {
|
|
return 0;
|
|
}
|
|
|
|
ExtCapOffset = 0;
|
|
|
|
do {
|
|
//
|
|
// Check if the extended capability register's capability id is USB Legacy Support.
|
|
//
|
|
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);
|
|
UsbSupportDw0.Dword = Data;
|
|
if ((Data & 0xFF) == XHC_CAP_USB_SUPPORTED_PROTOCOL) {
|
|
if (UsbSupportDw0.Data.RevMajor == MajorVersion) {
|
|
NameString = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET);
|
|
if (NameString == XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) {
|
|
//
|
|
// Ensure Name String field is xHCI supported protocols in xHCI Supported Protocol Capability Offset 04h
|
|
//
|
|
return ExtCapOffset;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// If not, then traverse all of the ext capability registers till finding out it.
|
|
//
|
|
NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);
|
|
ExtCapOffset += (NextExtCapReg << 2);
|
|
} while (NextExtCapReg != 0);
|
|
|
|
return 0xFFFFFFFF;
|
|
}
|
|
|
|
/**
|
|
Find PortSpeed value match Protocol Speed ID Value (PSIV).
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param ExtCapOffset The USB Major Version in xHCI Support Protocol Capability Field
|
|
@param PortSpeed The Port Speed Field in USB PortSc register
|
|
@param PortNumber The Port Number (0-indexed)
|
|
|
|
@return The Protocol Speed ID (PSI) from xHCI Supported Protocol capability register.
|
|
|
|
**/
|
|
UINT32
|
|
XhciPsivGetPsid (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 ExtCapOffset,
|
|
IN UINT8 PortSpeed,
|
|
IN UINT8 PortNumber
|
|
)
|
|
{
|
|
XHC_SUPPORTED_PROTOCOL_DW2 PortId;
|
|
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Reg;
|
|
UINT32 Count;
|
|
UINT32 MinPortIndex;
|
|
UINT32 MaxPortIndex;
|
|
|
|
if ((Xhc == NULL) || (ExtCapOffset == 0xFFFFFFFF)) {
|
|
return 0;
|
|
}
|
|
|
|
//
|
|
// According to XHCI 1.1 spec November 2017,
|
|
// Section 7.2 xHCI Supported Protocol Capability
|
|
// 1. Get the PSIC(Protocol Speed ID Count) value.
|
|
// 2. The PSID register boundary should be Base address + PSIC * 0x04
|
|
//
|
|
PortId.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_DW2_OFFSET);
|
|
|
|
//
|
|
// According to XHCI 1.1 spec November 2017, valid values
|
|
// for CompPortOffset are 1 to CompPortCount - 1.
|
|
//
|
|
// PortNumber is zero-indexed, so subtract 1.
|
|
//
|
|
if ((PortId.Data.CompPortOffset == 0) || (PortId.Data.CompPortCount == 0)) {
|
|
return 0;
|
|
}
|
|
|
|
MinPortIndex = PortId.Data.CompPortOffset - 1;
|
|
MaxPortIndex = MinPortIndex + PortId.Data.CompPortCount - 1;
|
|
|
|
if ((PortNumber < MinPortIndex) || (PortNumber > MaxPortIndex)) {
|
|
return 0;
|
|
}
|
|
|
|
for (Count = 0; Count < PortId.Data.Psic; Count++) {
|
|
Reg.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_PSI_OFFSET + (Count << 2));
|
|
if (Reg.Data.Psiv == PortSpeed) {
|
|
return Reg.Dword;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
Find PortSpeed value match case in XHCI Supported Protocol Capability
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param PortSpeed The Port Speed Field in USB PortSc register
|
|
@param PortNumber The Port Number (0-indexed)
|
|
|
|
@return The USB Port Speed.
|
|
|
|
**/
|
|
UINT16
|
|
XhcCheckUsbPortSpeedUsedPsic (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT8 PortSpeed,
|
|
IN UINT8 PortNumber
|
|
)
|
|
{
|
|
XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID SpField;
|
|
UINT16 UsbSpeedIdMap;
|
|
|
|
if (Xhc == NULL) {
|
|
return 0;
|
|
}
|
|
|
|
SpField.Dword = 0;
|
|
UsbSpeedIdMap = 0;
|
|
|
|
//
|
|
// Check xHCI Supported Protocol Capability, find the PSIV field to match
|
|
// PortSpeed definition when the Major Revision is 03h.
|
|
//
|
|
if (Xhc->Usb3SupOffset != 0xFFFFFFFF) {
|
|
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed, PortNumber);
|
|
if (SpField.Dword != 0) {
|
|
//
|
|
// Found the corresponding PORTSC value in PSIV field of USB3 offset.
|
|
//
|
|
UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Check xHCI Supported Protocol Capability, find the PSIV field to match
|
|
// PortSpeed definition when the Major Revision is 02h.
|
|
//
|
|
if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {
|
|
SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed, PortNumber);
|
|
if (SpField.Dword != 0) {
|
|
//
|
|
// Found the corresponding PORTSC value in PSIV field of USB2 offset.
|
|
//
|
|
if (SpField.Data.Psie == 2) {
|
|
//
|
|
// According to XHCI 1.1 spec November 2017,
|
|
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
|
|
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 2 shall represent bit rate in Mb/s
|
|
//
|
|
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM) {
|
|
//
|
|
// PSIM shows as default High-speed protocol, apply to High-speed mapping
|
|
//
|
|
UsbSpeedIdMap = USB_PORT_STAT_HIGH_SPEED;
|
|
}
|
|
} else if (SpField.Data.Psie == 1) {
|
|
//
|
|
// According to XHCI 1.1 spec November 2017,
|
|
// Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,
|
|
// PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 1 shall represent bit rate in Kb/s
|
|
//
|
|
if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM) {
|
|
//
|
|
// PSIM shows as default Low-speed protocol, apply to Low-speed mapping
|
|
//
|
|
UsbSpeedIdMap = USB_PORT_STAT_LOW_SPEED;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return UsbSpeedIdMap;
|
|
}
|
|
|
|
/**
|
|
Whether the XHCI host controller is halted.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
@retval TRUE The controller is halted.
|
|
@retval FALSE It isn't halted.
|
|
|
|
**/
|
|
BOOLEAN
|
|
XhcIsHalt (
|
|
IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);
|
|
}
|
|
|
|
/**
|
|
Whether system error occurred.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
@retval TRUE System error happened.
|
|
@retval FALSE No system error.
|
|
|
|
**/
|
|
BOOLEAN
|
|
XhcIsSysError (
|
|
IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
|
|
}
|
|
|
|
/**
|
|
Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.
|
|
|
|
The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).
|
|
This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
|
|
**/
|
|
VOID
|
|
XhcSetHsee (
|
|
IN USB_XHCI_INSTANCE *Xhc
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
|
UINT16 XhciCmd;
|
|
|
|
PciIo = Xhc->PciIo;
|
|
Status = PciIo->Pci.Read (
|
|
PciIo,
|
|
EfiPciIoWidthUint16,
|
|
PCI_COMMAND_OFFSET,
|
|
sizeof (XhciCmd) / sizeof (UINT16),
|
|
&XhciCmd
|
|
);
|
|
if (!EFI_ERROR (Status)) {
|
|
if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {
|
|
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
Reset the XHCI host controller.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@retval EFI_SUCCESS The XHCI host controller is reset.
|
|
@return Others Failed to reset the XHCI before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcResetHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
Status = EFI_SUCCESS;
|
|
|
|
DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));
|
|
//
|
|
// Host can only be reset when it is halt. If not so, halt it
|
|
//
|
|
if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {
|
|
Status = XhcHaltHC (Xhc, Timeout);
|
|
|
|
if (EFI_ERROR (Status)) {
|
|
return Status;
|
|
}
|
|
}
|
|
|
|
if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
|
|
((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))
|
|
{
|
|
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
|
|
//
|
|
// Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.
|
|
// Otherwise there may have the timeout case happened.
|
|
// The below is a workaround to solve such problem.
|
|
//
|
|
gBS->Stall (XHC_1_MILLISECOND);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
|
|
|
|
if (!EFI_ERROR (Status)) {
|
|
//
|
|
// The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.
|
|
// Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
|
|
//
|
|
XhcSetHsee (Xhc);
|
|
}
|
|
}
|
|
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Halt the XHCI host controller.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@return EFI_SUCCESS The XHCI host controller is halt.
|
|
@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcHaltHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);
|
|
return Status;
|
|
}
|
|
|
|
/**
|
|
Set the XHCI host controller to run.
|
|
|
|
@param Xhc The XHCI Instance.
|
|
@param Timeout Time to wait before abort (in millisecond, ms).
|
|
|
|
@return EFI_SUCCESS The XHCI host controller is running.
|
|
@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.
|
|
|
|
**/
|
|
EFI_STATUS
|
|
XhcRunHC (
|
|
IN USB_XHCI_INSTANCE *Xhc,
|
|
IN UINT32 Timeout
|
|
)
|
|
{
|
|
EFI_STATUS Status;
|
|
|
|
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);
|
|
Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);
|
|
return Status;
|
|
}
|