8b76f23534
RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME) with a new kind of virutal machines guest called a Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the confidentiality of TD memory contents and the TD's CPU state from other software, including the hosting Virtual-Machine Monitor (VMM), unless explicitly shared by the TD itself. Note: Intel TDX is only available on X64, so the Tdx related changes are in X64 path. In IA32 path, there may be null stub to make the build success. This patch includes below major changes. 1. Ia32/IntelTdx.asm IntelTdx.asm includes below routines used in ResetVector - IsTdx Check if the running system is Tdx guest. - InitTdxWorkarea It initialize the TDX_WORK_AREA. Because it is called by both BSP and APs and to avoid the race condition, only BSP can initialize the WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY is set. - ReloadFlat32 After reset all CPUs in TDX are initialized to 32-bit protected mode. But GDT register is not set. So this routine loads the GDT then jump to Flat 32 protected mode again. - InitTdx This routine wrap above 3 routines together to do Tdx initialization in ResetVector phase. - IsTdxEnabled It is a OneTimeCall to probe if TDX is enabled by checking the CC_WORK_AREA. - CheckTdxFeaturesBeforeBuildPagetables This routine is called to check if it is Non-TDX guest, TDX-Bsp or TDX-APs. Because in TDX guest all the initialization is done by BSP (including the page tables). APs should not build the tables. - TdxPostBuildPageTables It is called after Page Tables are built by BSP. byte[TDX_WORK_AREA_PGTBL_READY] is set by BSP to indicate APs can leave spin and go. 2. Ia32/PageTables64.asm As described above only the TDX BSP build the page tables. So PageTables64.asm is updated to make sure only TDX BSP build the PageTables. TDX APs will skip the page table building and set Cr3 directly. 3. Ia16/ResetVectorVtf0.asm In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). But in Non-Td guest the initial state of CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit real mode, then jump to the corresponding entry point. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
130 lines
4.2 KiB
NASM
130 lines
4.2 KiB
NASM
;------------------------------------------------------------------------------
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; @file
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; Sets the CR3 register for 64-bit paging
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;
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; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_PAT 0x080
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%define PAGE_GLOBAL 0x0100
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%define PAGE_2M_MBO 0x080
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%define PAGE_2M_PAT 0x01000
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%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define TDX_BSP 1
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%define TDX_AP 2
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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SetCr3ForPageTables64:
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; Check the TDX features.
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; If it is TDX APs, then jump to SetCr3 directly.
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; In TD guest the initialization is done by BSP, including building
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; the page tables. APs will spin on until byte[TDX_WORK_AREA_PGTBL_READY]
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; is set.
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OneTimeCall CheckTdxFeaturesBeforeBuildPagetables
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cmp eax, TDX_BSP
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je ClearOvmfPageTables
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cmp eax, TDX_AP
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je SetCr3
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; Check whether the SEV is active and populate the SevEsWorkArea
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OneTimeCall CheckSevFeatures
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; If SEV is enabled, the C-bit position is always above 31.
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; The mask will be saved in the EDX and applied during the
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; the page table build below.
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OneTimeCall GetSevCBitMaskAbove31
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ClearOvmfPageTables:
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;
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; For OVMF, build some initial page tables at
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; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
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;
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; This range should match with PcdOvmfSecPageTablesSize which is
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; declared in the FDF files.
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;
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; At the end of PEI, the pages tables will be rebuilt into a
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; more permanent location by DxeIpl.
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;
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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clearPageTablesMemoryLoop:
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mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
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loop clearPageTablesMemoryLoop
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (4)], edx
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1004)], edx
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x100C)], edx
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x1014)], edx
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (0x101C)], edx
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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pageTableEntriesLoop:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_2M_PDE_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
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loop pageTableEntriesLoop
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; Clear the C-bit from the GHCB page if the SEV-ES is enabled.
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OneTimeCall SevClearPageEncMaskForGhcbPage
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; TDX will do some PostBuildPages task, such as setting
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; byte[TDX_WORK_AREA_PGTBL_READY].
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OneTimeCall TdxPostBuildPageTables
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SetCr3:
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;
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; Set CR3 now that the paging structures are available
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;
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mov eax, PT_ADDR (0)
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mov cr3, eax
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OneTimeCallRet SetCr3ForPageTables64
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