a298a84478
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in PrmPkg. Cc: Andrew Fish <afish@apple.com> Cc: Kang Gao <kang.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Liu Yun <yun.y.liu@intel.com> Cc: Ankit Sinha <ankit.sinha@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com> Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
109 lines
2.9 KiB
C
109 lines
2.9 KiB
C
/** @file
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HPET register definitions from the IA-PC HPET (High Precision Event Timers)
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Specification, Revision 1.0a, October 2004.
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PRM Module Note:
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This specific header was copied from PcAtChipsetPkg to avoid a module dependency on the package
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just for this header. This is done for temporary testing purposes of the PRM module.
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Copyright (c) Microsoft Corporation
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Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef HPET_REGISTER_H_
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#define HPET_REGISTER_H_
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#define HPET_BASE_ADDRESS 0xFED00000
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#define HPET_RANGE_LENGTH 0x1000
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///
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/// HPET General Register Offsets
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///
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#define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000
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#define HPET_GENERAL_CONFIGURATION_OFFSET 0x010
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#define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020
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///
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/// HPET Timer Register Offsets
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///
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#define HPET_MAIN_COUNTER_OFFSET 0x0F0
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#define HPET_TIMER_CONFIGURATION_OFFSET 0x100
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#define HPET_TIMER_COMPARATOR_OFFSET 0x108
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#define HPET_TIMER_MSI_ROUTE_OFFSET 0x110
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///
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/// Stride between sets of HPET Timer Registers
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///
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#define HPET_TIMER_STRIDE 0x20
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#pragma pack(1)
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///
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/// HPET General Capabilities and ID Register
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///
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typedef union {
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struct {
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UINT32 Revision : 8;
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UINT32 NumberOfTimers : 5;
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UINT32 CounterSize : 1;
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UINT32 Reserved0 : 1;
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UINT32 LegacyRoute : 1;
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UINT32 VendorId : 16;
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UINT32 CounterClockPeriod : 32;
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} Bits;
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UINT64 Uint64;
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} HPET_GENERAL_CAPABILITIES_ID_REGISTER;
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///
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/// HPET General Configuration Register
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///
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typedef union {
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struct {
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UINT32 MainCounterEnable : 1;
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UINT32 LegacyRouteEnable : 1;
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UINT32 Reserved0 : 30;
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UINT32 Reserved1 : 32;
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} Bits;
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UINT64 Uint64;
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} HPET_GENERAL_CONFIGURATION_REGISTER;
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///
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/// HPET Timer Configuration Register
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///
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typedef union {
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struct {
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UINT32 Reserved0 : 1;
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UINT32 LevelTriggeredInterrupt : 1;
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UINT32 InterruptEnable : 1;
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UINT32 PeriodicInterruptEnable : 1;
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UINT32 PeriodicInterruptCapability : 1;
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UINT32 CounterSizeCapability : 1;
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UINT32 ValueSetEnable : 1;
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UINT32 Reserved1 : 1;
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UINT32 CounterSizeEnable : 1;
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UINT32 InterruptRoute : 5;
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UINT32 MsiInterruptEnable : 1;
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UINT32 MsiInterruptCapability : 1;
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UINT32 Reserved2 : 16;
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UINT32 InterruptRouteCapability;
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} Bits;
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UINT64 Uint64;
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} HPET_TIMER_CONFIGURATION_REGISTER;
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///
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/// HPET Timer MSI Route Register
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///
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typedef union {
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struct {
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UINT32 Value : 32;
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UINT32 Address : 32;
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} Bits;
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UINT64 Uint64;
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} HPET_TIMER_MSI_ROUTE_REGISTER;
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#pragma pack()
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#endif
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