705c3469b5
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add the RISC-V instance of the TimerLib. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Abner Chang <abner.chang@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ray Ni <ray.ni@Intel.com>
15 lines
389 B
Plaintext
15 lines
389 B
Plaintext
// /** @file
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// Base CPU Timer Library for RISC-V
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//
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// Copyright (c) 2023, Ventana Micro Systems Inc. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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// **/
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#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Timer Library"
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#string STR_MODULE_DESCRIPTION #language en-US "Provides basic timer support for RISC-V."
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