0d7601e546
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
156 lines
3.5 KiB
C
156 lines
3.5 KiB
C
/** @file
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C based implementation of IA32 interrupt handling only
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requiring a minimal assembly interrupt entry point.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "CpuDxe.h"
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#include "CpuGdt.h"
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//
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// Global descriptor table (GDT) Template
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//
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STATIC GDT_ENTRIES GdtTemplate = {
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//
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// NULL_SEL
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//
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{
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0x0, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x0, // type
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0x0, // limit 19:16, flags
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0x0, // base 31:24
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},
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//
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// LINEAR_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x092, // present, ring 0, data, read/write
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x09F, // present, ring 0, code, execute/read, conforming, accessed
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_DATA_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x093, // present, ring 0, data, read/write, accessed
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_CODE_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x09A, // present, ring 0, code, execute/read
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// SYS_CODE16_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x09A, // present, ring 0, code, execute/read
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0x08F, // page-granular, 16-bit
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0x0, // base 31:24
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},
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//
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// LINEAR_DATA64_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x092, // present, ring 0, data, read/write
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0x0CF, // page-granular, 32-bit
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0x0,
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},
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//
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// LINEAR_CODE64_SEL
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//
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{
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0x0FFFF, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x09A, // present, ring 0, code, execute/read
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0x0AF, // page-granular, 64-bit code
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0x0, // base (high)
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},
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//
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// SPARE5_SEL
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//
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{
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0x0, // limit 15:0
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0x0, // base 15:0
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0x0, // base 23:16
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0x0, // type
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0x0, // limit 19:16, flags
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0x0, // base 31:24
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},
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};
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/**
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Initialize Global Descriptor Table.
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**/
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VOID
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InitGlobalDescriptorTable (
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VOID
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)
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{
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GDT_ENTRIES *gdt;
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IA32_DESCRIPTOR gdtPtr;
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//
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// Allocate Runtime Data for the GDT
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//
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gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8);
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ASSERT (gdt != NULL);
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gdt = ALIGN_POINTER (gdt, 8);
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//
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// Initialize all GDT entries
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//
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CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate));
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//
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// Write GDT register
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//
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gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt;
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gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1);
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AsmWriteGdtr (&gdtPtr);
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//
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// Update selector (segment) registers base on new GDT
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//
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SetCodeSelector ((UINT16)CPU_CODE_SEL);
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SetDataSelectors ((UINT16)CPU_DATA_SEL);
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}
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