aa44e98dc2
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
693 lines
17 KiB
Plaintext
693 lines
17 KiB
Plaintext
/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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;* Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved *;
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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Scope(\)
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{
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//
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// Define VLV ABASE I/O as an ACPI operating region. The base address
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// can be found in Device 31, Registers 40-43h.
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//
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OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
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Field(PMIO, ByteAcc, NoLock, Preserve)
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{
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, 8,
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PWBS, 1, // Power Button Status
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Offset(0x20),
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, 13,
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PMEB, 1, // PME_B0_STS
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Offset(0x42), // General Purpose Control
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, 1,
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GPEC, 1
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}
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Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
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{
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Offset(0x20), // GPE0 Status
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, 4,
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PSCI, 1, // PUNIT SCI Status
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SCIS, 1 // GUNIT SCI Status
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}
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//
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// Define a Memory Region that will allow access to the PMC
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// Register Block. Note that in the Intel Reference Solution, the PMC
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// will get fixed up dynamically during POST.
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//
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OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
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Field(PMCR,DWordAcc,Lock,Preserve)
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{
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Offset(0x00), // Function Disable Register
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L10D, 1, // (0) LPIO1 DMA Disable
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L11D, 1, // (1) LPIO1 PWM #1 Disable
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L12D, 1, // (2) LPIO1 PWM #2 Disable
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L13D, 1, // (3) LPIO1 HS-UART #1 Disable
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L14D, 1, // (4) LPIO1 HS-UART #2 Disable
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L15D, 1, // (5) LPIO1 SPI Disable
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, 2, // (6:7) Reserved
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SD1D, 1, // (8) SCC SDIO #1 Disable
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SD2D, 1, // (9) SCC SDIO #2 Disable
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SD3D, 1, // (10) SCC SDIO #3 Disable
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HSID, 1, // (11)
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HDAD, 1, // (12) Azalia Disable
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LPED, 1, // (13) LPE Disable
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OTGD, 1, // (14) USB OTG Disable
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, 1, // (15) USH Disable
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, 1, // (16)
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, 1, // (17)
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, 1, // (18) USB Disable
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, 1, // (19) SEC Disable
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RP1D, 1, // (20) Root Port 0 Disable
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RP2D, 1, // (21) Root Port 1 Disable
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RP3D, 1, // (22) Root Port 2 Disable
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RP4D, 1, // (23) Root Port 3 Disable
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L20D, 1, // (24) LPIO2 DMA Disable
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L21D, 1, // (25) LPIO2 I2C #1 Disable
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L22D, 1, // (26) LPIO2 I2C #2 Disable
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L23D, 1, // (27) LPIO2 I2C #3 Disable
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L24D, 1, // (28) LPIO2 I2C #4 Disable
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L25D, 1, // (29) LPIO2 I2C #5 Disable
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L26D, 1, // (30) LPIO2 I2C #6 Disable
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L27D, 1 // (31) LPIO2 I2C #7 Disable
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}
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OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
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Field(CLKC,DWordAcc,Lock,Preserve)
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{
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Offset(0x00), // PLT_CLK_CTL_0
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CKC0, 2,
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CKF0, 1,
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, 29,
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Offset(0x04), // PLT_CLK_CTL_1
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CKC1, 2,
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CKF1, 1,
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, 29,
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Offset(0x08), // PLT_CLK_CTL_2
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CKC2, 2,
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CKF2, 1,
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, 29,
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Offset(0x0C), // PLT_CLK_CTL_3
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CKC3, 2,
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CKF3, 1,
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, 29,
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Offset(0x10), // PLT_CLK_CTL_4
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CKC4, 2,
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CKF4, 1,
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, 29,
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Offset(0x14), // PLT_CLK_CTL_5
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CKC5, 2,
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CKF5, 1,
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, 29,
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}
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} //end Scope(\)
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scope (\_SB)
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{
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Device(LPEA)
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{
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Name (_ADR, 0)
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Name (_HID, "80860F28")
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Name (_CID, "80860F28")
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//Name (_CLS, Package (3) {0x04, 0x01, 0x00})
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Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
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Name (_SUB, "80867270")
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Name (_UID, 1)
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Name (_DEP, Package() {\_SB.I2C2.RTEK})
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Name(_PR0,Package() {PLPE})
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Method (_STA, 0x0, NotSerialized)
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{
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If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
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{
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If(LEqual(LPAD, 1))
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{
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Return (0xF)
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}
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}
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Return (0x0)
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}
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Method (_DIS, 0x0, NotSerialized)
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{
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//Add a dummy disable function
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}
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0) // MMIO 1 - LPE MMIO
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Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
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GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} // Audio jack interrupt
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}
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)
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
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Store(LPE0, B0BA)
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CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
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Store(LPE1, B1BA)
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CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
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Store(LPE2, B2BA)
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Return (RBUF)
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}
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OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
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Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
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{
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Offset (0x84),
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PSAT, 32
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}
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PowerResource(PLPE, 0, 0) // Power Resource for LPEA
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{
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Method (_STA)
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{
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Return (1) // Power Resource is always available.
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}
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Method (_ON)
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{
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And(PSAT, 0xfffffffC, PSAT)
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OR(PSAT, 0X00000000, PSAT)
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}
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Method (_OFF)
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{
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OR(PSAT, 0x00000003, PSAT)
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OR(PSAT, 0X00000000, PSAT)
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}
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} // End PLPE
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} // End "Low Power Engine Audio"
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Device(LPA2)
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{
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Name (_ADR, 0)
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Name (_HID, "LPE0F28") // _HID: Hardware ID
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Name (_CID, "LPE0F28") // _CID: Compatible ID
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Name (_DDN, "Intel(R) SST Audio - LPE0F28") // _DDN: DOS Device Name
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Name (_SUB, "80867270")
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Name (_UID, 1)
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Name (_DEP, Package() {\_SB.I2C2.RTEK})
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Name(_PR0,Package() {PLPE})
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Method (_STA, 0x0, NotSerialized)
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{
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If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
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{
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If(LEqual(LPAD, 1))
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{
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Return (0xF)
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}
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}
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Return (0x0)
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}
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Method (_DIS, 0x0, NotSerialized)
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{
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//Add a dummy disable function
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}
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2) // LPE Memory Bar Allocate during post
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
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Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1) // MMIO 2 - Shadowed PCI Config Space
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}
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)
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Method (_CRS, 0x0, NotSerialized)
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{
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CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
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Add(LPE0, 0x140000, SHBA)
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CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
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Add(LPE0, 0x144000, MBBA)
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CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
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Add(LPE0, 0xC0000, IRBA)
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CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
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Add(LPE0, 0x100000, DRBA)
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CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
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Store(LPE1, B1BA)
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CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
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Store(LPE2, B2BA)
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Return (RBUF)
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}
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OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
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Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
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{
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Offset (0x84),
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PSAT, 32
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}
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PowerResource(PLPE, 0, 0) // Power Resource for LPEA
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{
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Method (_STA)
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{
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Return (1) // Power Resource is always available.
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}
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Method (_ON)
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{
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And(PSAT, 0xfffffffC, PSAT)
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OR(PSAT, 0X00000000, PSAT)
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}
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Method (_OFF)
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{
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OR(PSAT, 0x00000003, PSAT)
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OR(PSAT, 0X00000000, PSAT)
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}
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} // End PLPE
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Device (ADMA)
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{
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Name (_ADR, Zero) // _ADR: Address
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Name (_HID, "DMA0F28") // _HID: Hardware ID
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Name (_CID, "DMA0F28") // _CID: Compatible ID
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Name (_DDN, "Intel(R) Audio DMA0 - DMA0F28") // _DDN: DOS Device Name
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Name (_UID, One) // _UID: Unique ID
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0) // LPE BASE + LPE DMA0 offset
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Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM) // LPE BASE + LPE SHIM offset
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Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
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})
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Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
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{
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CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
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Add(LPE0, 0x98000, D0BA)
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CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
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Add(LPE0, 0x140000, SHBA)
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Return (RBUF)
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}
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}
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} // End "Low Power Engine Audio" for Android
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}
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scope (\_SB.PCI0)
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{
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//
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// Serial ATA Host Controller - Device 19, Function 0
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//
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Device(SATA)
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{
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Name(_ADR,0x00130000)
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//
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// SATA Methods pulled in via SSDT.
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//
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OperationRegion(SATR, PCI_Config, 0x74,0x4)
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Field(SATR,WordAcc,NoLock,Preserve)
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{
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Offset(0x00), // 0x74, PMCR
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, 8,
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PMEE, 1, //PME_EN
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, 6,
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PMES, 1 //PME_STS
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}
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Method (_STA, 0x0, NotSerialized)
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{
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Return(0xf)
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}
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Method(_DSW, 3)
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{
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} // End _DSW
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}
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//
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// For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
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//
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Device(EM41)
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{
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Name(_ADR,0x00100000)
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OperationRegion(SDIO, PCI_Config, 0x84,0x4)
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Field(SDIO,WordAcc,NoLock,Preserve)
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{
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Offset(0x00), // 0x84, PMCR
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, 8,
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PMEE, 1, //PME_EN
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, 6,
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PMES, 1 //PME_STS
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}
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Method (_STA, 0x0, NotSerialized)
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{
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If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
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{
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Return(0xF)
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}
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Else
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{
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Return(0x0)
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}
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}
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Method(_DSW, 3)
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{
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} // End _DSW
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method(_RMV, 0x0, NotSerialized)
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{
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Return (0)
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} // End _DSW
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}
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}
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//
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// For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
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//
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Device(EM45)
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{
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Name(_ADR,0x00170000)
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OperationRegion(SDIO, PCI_Config, 0x84,0x4)
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Field(SDIO,WordAcc,NoLock,Preserve)
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{
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Offset(0x00), // 0x84, PMCR
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, 8,
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PMEE, 1, //PME_EN
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, 6,
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PMES, 1 //PME_STS
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}
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Method (_STA, 0x0, NotSerialized)
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{
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If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
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{
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Return(0xF)
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}
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Else
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{
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Return(0x0)
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}
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}
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Method(_DSW, 3)
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{
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} // End _DSW
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method(_RMV, 0x0, NotSerialized)
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{
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Return (0)
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} // End _DSW
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}
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}
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//
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// For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
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//
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Device(SD12)
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{
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Name(_ADR,0x00120000)
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Method (_STA, 0x0, NotSerialized)
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{
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//
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// PCIM>> 0:ACPI mode 1:PCI mode
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//
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If (LEqual(PCIM, 0)) {
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Return (0x0)
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}
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//
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// If device is disabled.
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//
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If (LEqual(SD3D, 1))
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{
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Return (0x0)
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}
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Return (0xF)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method(_RMV, 0x0, NotSerialized)
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{
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// SDRM = 0 non-removable;
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If (LEqual(SDRM, 0))
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{
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Return (0)
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}
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Return (1)
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}
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}
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}
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// xHCI Controller - Device 20, Function 0
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include("PchXhci.asl")
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//
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// High Definition Audio Controller - Device 27, Function 0
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//
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Device(HDEF)
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{
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Name(_ADR, 0x001B0000)
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include("PchAudio.asl")
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Method (_STA, 0x0, NotSerialized)
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{
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If (LEqual(HDAD, 0))
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{
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Return(0xf)
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}
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Return(0x0)
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}
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Method(_DSW, 3)
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{
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} // End _DSW
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} // end "High Definition Audio Controller"
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//
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// PCIE Root Port #1
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//
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Device(RP01)
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{
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Name(_ADR, 0x001C0000)
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include("PchPcie.asl")
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Name(_PRW, Package() {9, 4})
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Method(_PRT,0)
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{
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If(PICM) { Return(AR04) }// APIC mode
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Return (PR04) // PIC Mode
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} // end _PRT
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} // end "PCIE Root Port #1"
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//
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// PCIE Root Port #2
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//
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Device(RP02)
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{
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Name(_ADR, 0x001C0001)
|
|
include("PchPcie.asl")
|
|
Name(_PRW, Package() {9, 4})
|
|
|
|
Method(_PRT,0)
|
|
{
|
|
If(PICM) { Return(AR05) }// APIC mode
|
|
Return (PR05) // PIC Mode
|
|
} // end _PRT
|
|
|
|
} // end "PCIE Root Port #2"
|
|
|
|
//
|
|
// PCIE Root Port #3
|
|
//
|
|
Device(RP03)
|
|
{
|
|
Name(_ADR, 0x001C0002)
|
|
include("PchPcie.asl")
|
|
Name(_PRW, Package() {9, 4})
|
|
Method(_PRT,0)
|
|
{
|
|
If(PICM) { Return(AR06) }// APIC mode
|
|
Return (PR06) // PIC Mode
|
|
} // end _PRT
|
|
|
|
} // end "PCIE Root Port #3"
|
|
|
|
//
|
|
// PCIE Root Port #4
|
|
//
|
|
Device(RP04)
|
|
{
|
|
Name(_ADR, 0x001C0003)
|
|
include("PchPcie.asl")
|
|
Name(_PRW, Package() {9, 4})
|
|
Method(_PRT,0)
|
|
{
|
|
If(PICM) { Return(AR07) }// APIC mode
|
|
Return (PR07) // PIC Mode
|
|
} // end _PRT
|
|
|
|
} // end "PCIE Root Port #4"
|
|
|
|
|
|
Scope(\_SB)
|
|
{
|
|
//
|
|
// Dummy power resource for USB D3 cold support
|
|
//
|
|
PowerResource(USBC, 0, 0)
|
|
{
|
|
Method(_STA) { Return (0xF) }
|
|
Method(_ON) {}
|
|
Method(_OFF) {}
|
|
}
|
|
}
|
|
//
|
|
// EHCI Controller - Device 29, Function 0
|
|
//
|
|
Device(EHC1)
|
|
{
|
|
Name(_ADR, 0x001D0000)
|
|
Name(_DEP, Package(0x1)
|
|
{
|
|
PEPD
|
|
})
|
|
include("PchEhci.asl")
|
|
Name(_PRW, Package() {0x0D, 4})
|
|
|
|
OperationRegion(USBR, PCI_Config, 0x54,0x4)
|
|
Field(USBR,WordAcc,NoLock,Preserve)
|
|
{
|
|
Offset(0x00), // 0x54, PMCR
|
|
, 8,
|
|
PMEE, 1, //PME_EN
|
|
, 6,
|
|
PMES, 1 //PME_STS
|
|
}
|
|
|
|
Method (_STA, 0x0, NotSerialized)
|
|
{
|
|
If(LEqual(XHCI, 0)) //XHCI is not present. It means EHCI is there
|
|
{
|
|
Return (0xF)
|
|
} Else
|
|
{
|
|
Return (0x0)
|
|
}
|
|
}
|
|
|
|
Method (_RMV, 0, NotSerialized)
|
|
{
|
|
Return (0x0)
|
|
}
|
|
//
|
|
// Create a dummy PR3 method to indicate to the PCI driver
|
|
// that the device is capable of D3 cold
|
|
//
|
|
Method(_PR3, 0x0, NotSerialized)
|
|
{
|
|
return (Package() {\_SB.USBC})
|
|
}
|
|
|
|
} // end "EHCI Controller"
|
|
|
|
//
|
|
// SMBus Controller - Device 31, Function 3
|
|
//
|
|
Device(SBUS)
|
|
{
|
|
Name(_ADR,0x001F0003)
|
|
Include("PchSmb.asl")
|
|
}
|
|
|
|
Device(SEC0)
|
|
{
|
|
Name (_ADR, 0x001a0000) // Device 0x1a, Function 0
|
|
Name(_DEP, Package(0x1)
|
|
{
|
|
PEPD
|
|
})
|
|
|
|
|
|
OperationRegion (PMEB, PCI_Config, 0x84, 0x04) //PMECTRLSTATUS
|
|
Field (PMEB, WordAcc, NoLock, Preserve)
|
|
{
|
|
, 8,
|
|
PMEE, 1, //bit8 PMEENABLE
|
|
, 6,
|
|
PMES, 1 //bit15 PMESTATUS
|
|
}
|
|
|
|
// Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
|
|
// Arg1 -- integer that contains target system state (0-4)
|
|
// Arg2 -- integer that contains the target device state
|
|
Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake
|
|
{
|
|
}
|
|
|
|
Method (_CRS, 0, NotSerialized)
|
|
{
|
|
Name (RBUF, ResourceTemplate ()
|
|
{
|
|
Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
|
|
})
|
|
|
|
If (LEqual(PAVP, 2))
|
|
{
|
|
Return (RBUF)
|
|
}
|
|
Return (ResourceTemplate() {})
|
|
}
|
|
|
|
Method (_STA)
|
|
{
|
|
If (LNotEqual(PAVP, 0))
|
|
{
|
|
Return (0xF)
|
|
}
|
|
Return (0x0)
|
|
}
|
|
} // Device(SEC0)
|
|
|
|
} // End scope (\_SB.PCI0)
|
|
|