0ff5aa9cae
If Stack Guard is enabled and there's really a stack overflow happened during boot, a Page Fault exception will be triggered. Because the stack is out of usage, the exception handler, which shares the stack with normal UEFI driver, cannot be executed and cannot dump the processor information. Without those information, it's very difficult for the BIOS developers locate the root cause of stack overflow. And without a workable stack, the developer cannot event use single step to debug the UEFI driver with JTAG debugger. In order to make sure the exception handler to execute normally after stack overflow. We need separate stacks for exception handlers in case of unusable stack. IA processor allows to switch to a new stack during handling interrupt and exception. But X64 and IA32 provides different ways to make it. X64 provides interrupt stack table (IST) to allow maximum 7 different exceptions to have new stack for its handler. IA32 doesn't have IST mechanism and can only use task gate to do it since task switch allows to load a new stack through its task-state segment (TSS). The new API, InitializeCpuExceptionHandlersEx, is implemented to complete extra initialization for stack switch of exception handler. Since setting up stack switch needs allocating new memory for new stack, new GDT table and task-state segment but the initialization method will be called in different phases which have no consistent way to reserve those memory, this new API is allowed to pass the reserved resources to complete the extra works. This is cannot be done by original InitializeCpuExceptionHandlers. Considering exception handler initialization for MP situation, this new API is also necessary, because AP is not supposed to allocate memory. So the memory needed for stack switch have to be reserved in BSP before waking up AP and then pass them to InitializeCpuExceptionHandlersEx afterwards. Since Stack Guard feature is available only for DXE phase at this time, the new API is fully implemented for DXE only. Other phases implement a dummy one which just calls InitializeCpuExceptionHandlers(). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Jiewen.yao@intel.com
399 lines
11 KiB
NASM
399 lines
11 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; ExceptionTssEntryAsm.Asm
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;
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; Abstract:
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;
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; IA32 CPU Exception Handler with Separate Stack
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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;
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; IA32 TSS Memory Layout Description
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;
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struc IA32_TSS
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resw 1
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resw 1
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.ESP0: resd 1
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.SS0: resw 1
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resw 1
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.ESP1: resd 1
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.SS1: resw 1
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resw 1
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.ESP2: resd 1
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.SS2: resw 1
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resw 1
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._CR3: resd 1
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.EIP: resd 1
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.EFLAGS: resd 1
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._EAX: resd 1
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._ECX: resd 1
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._EDX: resd 1
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._EBX: resd 1
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._ESP: resd 1
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._EBP: resd 1
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._ESI: resd 1
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._EDI: resd 1
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._ES: resw 1
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resw 1
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._CS: resw 1
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resw 1
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._SS: resw 1
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resw 1
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._DS: resw 1
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resw 1
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._FS: resw 1
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resw 1
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._GS: resw 1
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resw 1
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.LDT: resw 1
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resw 1
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resw 1
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resw 1
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endstruc
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;
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; CommonExceptionHandler()
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;
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extern ASM_PFX(CommonExceptionHandler)
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SECTION .data
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SECTION .text
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ALIGN 8
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;
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; Exception handler stub table
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;
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AsmExceptionEntryBegin:
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%assign Vector 0
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%rep 32
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DoIret%[Vector]:
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iretd
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ASM_PFX(ExceptionTaskSwtichEntry%[Vector]):
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db 0x6a ; push #VectorNum
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db %[Vector]
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mov eax, ASM_PFX(CommonTaskSwtichEntryPoint)
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call eax
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mov esp, eax ; Restore stack top
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jmp DoIret%[Vector]
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%assign Vector Vector+1
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%endrep
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AsmExceptionEntryEnd:
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;
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; Common part of exception handler
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;
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global ASM_PFX(CommonTaskSwtichEntryPoint)
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ASM_PFX(CommonTaskSwtichEntryPoint):
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;
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; Stack:
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; +---------------------+ <-- EBP - 8
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; + TSS Base +
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; +---------------------+ <-- EBP - 4
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; + CPUID.EDX +
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; +---------------------+ <-- EBP
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; + EIP +
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; +---------------------+ <-- EBP + 4
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; + Vector Number +
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; +---------------------+ <-- EBP + 8
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; + Error Code +
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; +---------------------+
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;
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mov ebp, esp ; Stack frame
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; Use CPUID to determine if FXSAVE/FXRESTOR and DE are supported
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mov eax, 1
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cpuid
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push edx
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; Get TSS base of interrupted task through PreviousTaskLink field in
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; current TSS base
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sub esp, 8
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sgdt [esp + 2]
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mov eax, [esp + 4] ; GDT base
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add esp, 8
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xor ebx, ebx
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str bx ; Current TR
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mov ecx, [eax + ebx + 2]
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shl ecx, 8
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mov cl, [eax + ebx + 7]
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ror ecx, 8 ; ecx = Current TSS base
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push ecx ; keep it in stack for later use
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movzx ebx, word [ecx] ; Previous Task Link
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mov ecx, [eax + ebx + 2]
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shl ecx, 8
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mov cl, [eax + ebx + 7]
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ror ecx, 8 ; ecx = Previous TSS base
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;
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; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32
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; is 16-byte aligned
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;
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and esp, 0xfffffff0
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sub esp, 12
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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push dword [ecx + IA32_TSS._EAX]
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push dword [ecx + IA32_TSS._ECX]
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push dword [ecx + IA32_TSS._EDX]
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push dword [ecx + IA32_TSS._EBX]
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push dword [ecx + IA32_TSS._ESP]
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push dword [ecx + IA32_TSS._EBP]
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push dword [ecx + IA32_TSS._ESI]
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push dword [ecx + IA32_TSS._EDI]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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movzx eax, word [ecx + IA32_TSS._SS]
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push eax
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movzx eax, word [ecx + IA32_TSS._CS]
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push eax
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movzx eax, word [ecx + IA32_TSS._DS]
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push eax
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movzx eax, word [ecx + IA32_TSS._ES]
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push eax
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movzx eax, word [ecx + IA32_TSS._FS]
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push eax
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movzx eax, word [ecx + IA32_TSS._GS]
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push eax
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;; UINT32 Eip;
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push dword [ecx + IA32_TSS.EIP]
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;; UINT32 Gdtr[2], Idtr[2];
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sub esp, 8
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sidt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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sub esp, 8
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sgdt [esp]
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mov eax, [esp + 2]
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xchg eax, [esp]
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and eax, 0xFFFF
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mov [esp+4], eax
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;; UINT32 Ldtr, Tr;
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mov eax, ebx ; ebx still keeps selector of interrupted task
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push eax
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movzx eax, word [ecx + IA32_TSS.LDT]
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push eax
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;; UINT32 EFlags;
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push dword [ecx + IA32_TSS.EFLAGS]
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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mov eax, cr4
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push eax ; push cr4 firstly
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mov edx, [ebp - 4] ; cpuid.edx
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz .1
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or eax, BIT9 ; Set CR4.OSFXSR
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.1:
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test edx, BIT2 ; Test for Debugging Extensions support
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jz .2
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or eax, BIT3 ; Set CR4.DE
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.2:
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mov cr4, eax
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mov eax, cr3
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push eax
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mov eax, cr2
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push eax
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xor eax, eax
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push eax
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mov eax, cr0
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push eax
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov eax, dr7
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push eax
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mov eax, dr6
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push eax
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mov eax, dr3
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push eax
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mov eax, dr2
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push eax
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mov eax, dr1
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push eax
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mov eax, dr0
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push eax
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;; FX_SAVE_STATE_IA32 FxSaveState;
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;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)
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;; when executing fxsave/fxrstor instruction
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
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; edx still contains result from CPUID above
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jz .3
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clts
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sub esp, 512
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mov edi, esp
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db 0xf, 0xae, 0x7 ;fxsave [edi]
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.3:
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;; UINT32 ExceptionData;
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push dword [ebp + 8]
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;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
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cld
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;; call into exception handler
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mov esi, ecx ; Keep TSS base to avoid overwrite
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mov eax, ASM_PFX(CommonExceptionHandler)
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;; Prepare parameter and call
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mov edx, esp
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push edx ; EFI_SYSTEM_CONTEXT
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push dword [ebp + 4] ; EFI_EXCEPTION_TYPE (vector number)
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;
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; Call External Exception Handler
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;
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call eax
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add esp, 8 ; Restore stack before calling
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mov ecx, esi ; Restore TSS base
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;; UINT32 ExceptionData;
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add esp, 4
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;; FX_SAVE_STATE_IA32 FxSaveState;
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mov edx, [ebp - 4] ; cpuid.edx
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz .4
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mov esi, esp
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db 0xf, 0xae, 0xe ; fxrstor [esi]
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.4:
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add esp, 512
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support debuggers
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;; that set breakpoints in interrupt/exception context
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add esp, 4 * 6
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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pop eax
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mov cr0, eax
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add esp, 4 ; not for Cr1
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pop eax
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mov cr2, eax
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pop eax
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mov dword [ecx + IA32_TSS._CR3], eax
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pop eax
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mov cr4, eax
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;; UINT32 EFlags;
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pop dword [ecx + IA32_TSS.EFLAGS]
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mov ebx, dword [ecx + IA32_TSS.EFLAGS]
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btr ebx, 9 ; Do 'cli'
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mov dword [ecx + IA32_TSS.EFLAGS], ebx
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;; UINT32 Ldtr, Tr;
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;; UINT32 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add esp, 24
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;; UINT32 Eip;
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pop dword [ecx + IA32_TSS.EIP]
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;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;
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;; NOTE - modified segment registers could hang the debugger... We
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;; could attempt to insulate ourselves against this possibility,
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;; but that poses risks as well.
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;;
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pop eax
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o16 mov [ecx + IA32_TSS._GS], ax
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pop eax
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o16 mov [ecx + IA32_TSS._FS], ax
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pop eax
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o16 mov [ecx + IA32_TSS._ES], ax
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pop eax
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o16 mov [ecx + IA32_TSS._DS], ax
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pop eax
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o16 mov [ecx + IA32_TSS._CS], ax
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pop eax
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o16 mov [ecx + IA32_TSS._SS], ax
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;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;
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pop dword [ecx + IA32_TSS._EDI]
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pop dword [ecx + IA32_TSS._ESI]
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add esp, 4 ; not for ebp
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add esp, 4 ; not for esp
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pop dword [ecx + IA32_TSS._EBX]
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pop dword [ecx + IA32_TSS._EDX]
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pop dword [ecx + IA32_TSS._ECX]
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pop dword [ecx + IA32_TSS._EAX]
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; Set single step DB# to allow debugger to able to go back to the EIP
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; where the exception is triggered.
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;; Create return context for iretd in stub function
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mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
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mov ebx, dword [ecx + IA32_TSS.EIP]
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mov [eax - 0xc], ebx ; create EIP in old stack
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movzx ebx, word [ecx + IA32_TSS._CS]
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mov [eax - 0x8], ebx ; create CS in old stack
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mov ebx, dword [ecx + IA32_TSS.EFLAGS]
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bts ebx, 8
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mov [eax - 0x4], ebx ; create eflags in old stack
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mov dword [ecx + IA32_TSS.EFLAGS], ebx ; update eflags in old TSS
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mov eax, dword [ecx + IA32_TSS._ESP] ; Get old stack pointer
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sub eax, 0xc ; minus 12 byte
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mov dword [ecx + IA32_TSS._ESP], eax ; Set new stack pointer
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;; Replace the EIP of interrupted task with stub function
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mov eax, ASM_PFX(SingleStepStubFunction)
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mov dword [ecx + IA32_TSS.EIP], eax
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mov ecx, [ebp - 8] ; Get current TSS base
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mov eax, dword [ecx + IA32_TSS._ESP] ; Return current stack top
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mov esp, ebp
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ret
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global ASM_PFX(SingleStepStubFunction)
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ASM_PFX(SingleStepStubFunction):
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;
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; we need clean TS bit in CR0 to execute
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; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.
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;
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clts
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iretd
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global ASM_PFX(AsmGetTssTemplateMap)
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ASM_PFX(AsmGetTssTemplateMap):
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push ebp ; C prolog
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mov ebp, esp
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pushad
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mov ebx, dword [ebp + 0x8]
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mov dword [ebx], ASM_PFX(ExceptionTaskSwtichEntry0)
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mov dword [ebx + 0x4], (AsmExceptionEntryEnd - AsmExceptionEntryBegin) / 32
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mov dword [ebx + 0x8], 0
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popad
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pop ebp
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ret
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