4c34a8ea19
Replace hard-coded machine code with equivalent assembly source code. Changes tested by checking for machine code equivalence by disassembling the original and changed code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin <chris.ruffin@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
176 lines
5.1 KiB
NASM
176 lines
5.1 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; SmiException.nasm
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;
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; Abstract:
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;
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; Exception handlers used in SM mode
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;
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;-------------------------------------------------------------------------------
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global ASM_PFX(gcStmPsd)
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extern ASM_PFX(SmmStmExceptionHandler)
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extern ASM_PFX(SmmStmSetup)
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extern ASM_PFX(SmmStmTeardown)
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extern ASM_PFX(gStmXdSupported)
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extern ASM_PFX(gStmSmiHandlerIdtr)
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%define MSR_IA32_MISC_ENABLE 0x1A0
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%define MSR_EFER 0xc0000080
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%define MSR_EFER_XD 0x800
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CODE_SEL equ 0x08
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DATA_SEL equ 0x20
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TSS_SEL equ 0x40
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SECTION .data
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ASM_PFX(gcStmPsd):
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DB 'TXTPSSIG'
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DW PSD_SIZE
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DW 1 ; Version
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DD 0 ; LocalApicId
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DB 0x05 ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr
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DB 0 ; BIOS to STM
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DB 0 ; STM to BIOS
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DB 0
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DW CODE_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW DATA_SEL
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DW TSS_SEL
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DW 0
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DQ 0 ; SmmCr3
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DD ASM_PFX(OnStmSetup)
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DD 0
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DD ASM_PFX(OnStmTeardown)
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DD 0
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DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint
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DQ 0 ; SmmSmiHandlerRsp
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DQ 0
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DD 0
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DD 0x80010100 ; RequiredStmSmmRevId
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DD ASM_PFX(OnException)
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DD 0
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DQ 0 ; ExceptionStack
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DW DATA_SEL
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DW 0x01F ; ExceptionFilter
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DD 0
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DD 0
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DD 0
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DQ 0 ; BiosHwResourceRequirementsPtr
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DQ 0 ; AcpiRsdp
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DB 0 ; PhysicalAddressBits
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PSD_SIZE equ $ - ASM_PFX(gcStmPsd)
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SECTION .text
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;------------------------------------------------------------------------------
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; SMM Exception handlers
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;------------------------------------------------------------------------------
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global ASM_PFX(OnException)
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ASM_PFX(OnException):
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mov ecx, esp
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push ecx
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call ASM_PFX(SmmStmExceptionHandler)
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add esp, 4
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mov ebx, eax
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mov eax, 4
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vmcall
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jmp $
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global ASM_PFX(OnStmSetup)
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ASM_PFX(OnStmSetup):
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;
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; Check XD disable bit
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;
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xor esi, esi
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz @StmXdDone1
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .51
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.51:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone1:
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push esi
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call ASM_PFX(SmmStmSetup)
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz .71
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pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .71
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.71:
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rsm
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global ASM_PFX(OnStmTeardown)
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ASM_PFX(OnStmTeardown):
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;
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; Check XD disable bit
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;
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xor esi, esi
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz @StmXdDone2
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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mov esi, edx ; save MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
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jz .52
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and dx, 0xFFFB ; clear XD Disable bit if it is set
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wrmsr
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.52:
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mov ecx, MSR_EFER
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rdmsr
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or ax, MSR_EFER_XD ; enable NXE
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wrmsr
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@StmXdDone2:
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push esi
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call ASM_PFX(SmmStmTeardown)
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mov eax, ASM_PFX(gStmXdSupported)
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mov al, [eax]
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cmp al, 0
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jz .72
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pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
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test edx, BIT2
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jz .72
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mov ecx, MSR_IA32_MISC_ENABLE
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rdmsr
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or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
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wrmsr
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.72:
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rsm
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