5cc45b70c3
The idea is to keep ArmPkg responsible for the ARM architectural modules and ArmPlatformPkg the ARM development platform packages (with their respective drivers). ArmPlatformPkg: Reduce driver dependency on ArmPlatform.h - Move some driver definitions from C-Macro to PCD values - Unify PCD driver namespace git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11956 6f19259b-4bc3-4df7-8a09-765794883524
80 lines
3.0 KiB
C
80 lines
3.0 KiB
C
/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef L2CACHELIB_H_
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#define L2CACHELIB_H_
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#define L2X0_CACHEID 0x000
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#define L2X0_CTRL 0x100
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#define L2X0_AUXCTRL 0x104
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#define L230_TAG_LATENCY 0x108
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#define L230_DATA_LATENCY 0x10C
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#define L2X0_INTCLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_INVWAY 0x77C
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_PFCTRL 0xF60
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#define L2X0_PWRCTRL 0xF80
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#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
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#define L2X0_CACHEID_PARTNUM_PL310 0x03
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#define L2X0_CTRL_ENABLED 0x1
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#define L2X0_CTRL_DISABLED 0x0
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#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)
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#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)
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#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)
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#define L2X0_AUXCTRL_EM (1 << 20)
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#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)
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#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)
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#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)
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#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)
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#define L2X0_AUXCTRL_SBO (1 << 25)
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#define L2X0_AUXCTRL_NSAC (1 << 27)
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#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
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#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
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#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)
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#define L2x0_LATENCY_1_CYCLE 0
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#define L2x0_LATENCY_2_CYCLES 1
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#define L2x0_LATENCY_3_CYCLES 2
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#define L2x0_LATENCY_4_CYCLES 3
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#define L2x0_LATENCY_5_CYCLES 4
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#define L2x0_LATENCY_6_CYCLES 5
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#define L2x0_LATENCY_7_CYCLES 6
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#define L2x0_LATENCY_8_CYCLES 7
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#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))
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#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
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#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
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VOID
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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);
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#endif /* L2CACHELIB_H_ */
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