f4dfad05dd
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
115 lines
3.0 KiB
ArmAsm
115 lines
3.0 KiB
ArmAsm
#
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#
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#include <Chipset/AArch64.h>
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#include <AsmMacroIoLibV8.h>
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#include <Base.h>
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#include <AutoGen.h>
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.text
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//============================================================
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//Default Exception Handlers
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//============================================================
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#define TO_HANDLER \
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EL1_OR_EL2(x1) \
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1: mrs x1, elr_el1 /* EL1 Exception Link Register */ ;\
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b 3f ;\
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2: mrs x1, elr_el2 /* EL2 Exception Link Register */ ;\
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3: bl ASM_PFX(PeiCommonExceptionEntry) ;
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//
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// Default Exception handlers: There is no plan to return from any of these exceptions.
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// No context saving at all.
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//
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VECTOR_BASE(PeiVectorTable)
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
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_DefaultSyncExceptHandler_t:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
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_DefaultIrq_t:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
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_DefaultFiq_t:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SP0_SERR)
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_DefaultSError_t:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
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_DefaultSyncExceptHandler_h:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
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_DefaultIrq_h:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
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_DefaultFiq_h:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_CUR_SPx_SERR)
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_DefaultSError_h:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SYNC)
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_DefaultSyncExceptHandler_LowerA64:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_IRQ)
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_DefaultIrq_LowerA64:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_FIQ)
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_DefaultFiq_LowerA64:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A64_SERR)
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_DefaultSError_LowerA64:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SYNC)
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_DefaultSyncExceptHandler_LowerA32:
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mov x0, #EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_IRQ)
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_DefaultIrq_LowerA32:
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mov x0, #EXCEPT_AARCH64_IRQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_FIQ)
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_DefaultFiq_LowerA32:
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mov x0, #EXCEPT_AARCH64_FIQ
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TO_HANDLER
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VECTOR_ENTRY(PeiVectorTable, ARM_VECTOR_LOW_A32_SERR)
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_DefaultSError_LowerA32:
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mov x0, #EXCEPT_AARCH64_SERROR
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TO_HANDLER
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VECTOR_END(PeiVectorTable)
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