9344f09215
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
320 lines
10 KiB
NASM
320 lines
10 KiB
NASM
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#include "BaseLibInternals.h"
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; Thunk.asm
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;
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; Abstract:
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;
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; Real mode thunk
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;
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;------------------------------------------------------------------------------
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global ASM_PFX(m16Size)
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global ASM_PFX(mThunk16Attr)
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global ASM_PFX(m16Gdt)
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global ASM_PFX(m16GdtrBase)
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global ASM_PFX(mTransition)
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global ASM_PFX(m16Start)
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struc IA32_REGS
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._EDI: resd 1
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._ESI: resd 1
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._EBP: resd 1
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._ESP: resd 1
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._EBX: resd 1
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._EDX: resd 1
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._ECX: resd 1
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._EAX: resd 1
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._DS: resw 1
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._ES: resw 1
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._FS: resw 1
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._GS: resw 1
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._EFLAGS: resq 1
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._EIP: resd 1
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._CS: resw 1
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._SS: resw 1
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.size:
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endstruc
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SECTION .data
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;
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; These are global constant to convey information to C code.
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;
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ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
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ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
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ASM_PFX(m16Gdt) DW _NullSeg - ASM_PFX(m16Start)
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ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
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ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
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SECTION .text
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ASM_PFX(m16Start):
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SavedGdt:
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dw 0
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dq 0
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;------------------------------------------------------------------------------
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; _BackFromUserCode() takes control in real mode after 'retf' has been executed
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; by user code. It will be shadowed to somewhere in memory below 1MB.
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;------------------------------------------------------------------------------
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_BackFromUserCode:
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;
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; The order of saved registers on the stack matches the order they appears
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; in IA32_REGS structure. This facilitates wrapper function to extract them
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; into that structure.
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;
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BITS 16
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push ss
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push cs
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;
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; Note: We can't use o32 on the next instruction because of a bug
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; in NASM 2.09.04 through 2.10rc1.
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;
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call dword .Base ; push eip
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.Base:
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push dword 0 ; reserved high order 32 bits of EFlags
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pushfd
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cli ; disable interrupts
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push gs
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push fs
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push es
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push ds
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pushad
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mov edx, strict dword 0
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.ThunkAttrEnd:
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test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
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jz .1
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mov ax, 2401h
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int 15h
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cli ; disable interrupts
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jnc .2
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.1:
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test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
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jz .2
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in al, 92h
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or al, 2
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out 92h, al ; deactivate A20M#
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.2:
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xor eax, eax
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mov ax, ss
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lea ebp, [esp + IA32_REGS.size]
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mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
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mov ebx, [bp - IA32_REGS.size + IA32_REGS._EIP]
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shl eax, 4 ; shl eax, 4
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add ebp, eax ; add ebp, eax
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mov eax, cs
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shl eax, 4
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lea eax, [eax + ebx + (.X64JmpEnd - .Base)]
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mov [cs:bx + (.X64JmpEnd - 6 - .Base)], eax
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mov eax, strict dword 0
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.SavedCr4End:
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mov cr4, eax
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o32 lgdt [cs:bx + (SavedGdt - .Base)]
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mov ecx, 0c0000080h
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rdmsr
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or ah, 1
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wrmsr
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mov eax, strict dword 0
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.SavedCr0End:
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mov cr0, eax
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jmp 0:strict dword 0
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.X64JmpEnd:
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BITS 64
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nop
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mov rsp, strict qword 0
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.SavedSpEnd:
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nop
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ret
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_EntryPoint:
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DD _ToUserCode - ASM_PFX(m16Start)
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DW CODE16
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_16Gdtr:
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DW GDT_SIZE - 1
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_16GdtrBase:
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DQ 0
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_16Idtr:
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DW (1 << 10) - 1
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DD 0
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;------------------------------------------------------------------------------
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; _ToUserCode() takes control in real mode before passing control to user code.
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; It will be shadowed to somewhere in memory below 1MB.
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;------------------------------------------------------------------------------
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_ToUserCode:
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BITS 16
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mov ss, dx ; set new segment selectors
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mov ds, dx
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mov es, dx
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mov fs, dx
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mov gs, dx
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mov ecx, 0c0000080h
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mov cr0, eax ; real mode starts at next instruction
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rdmsr
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and ah, ~1
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wrmsr
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mov cr4, ebp
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mov ss, si ; set up 16-bit stack segment
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mov esp, ebx ; set up 16-bit stack pointer
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call dword .Base ; push eip
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.Base:
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pop ebp ; ebp <- address of .Base
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push word [dword esp + IA32_REGS.size + 2]
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lea ax, [bp + (.RealMode - .Base)]
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push ax
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retf ; execution begins at next instruction
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.RealMode:
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o32 lidt [cs:bp + (_16Idtr - .Base)]
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popad
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pop ds
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pop es
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pop fs
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pop gs
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popfd
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lea esp, [esp + 4] ; skip high order 32 bits of EFlags
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o32 retf ; transfer control to user code
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ALIGN 8
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CODE16 equ _16Code - $
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DATA16 equ _16Data - $
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DATA32 equ _32Data - $
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_NullSeg DQ 0
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_16Code:
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DW -1
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DW 0
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DB 0
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DB 9bh
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DB 8fh ; 16-bit segment, 4GB limit
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DB 0
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_16Data:
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DW -1
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DW 0
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DB 0
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DB 93h
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DB 8fh ; 16-bit segment, 4GB limit
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DB 0
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_32Data:
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DW -1
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DW 0
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DB 0
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DB 93h
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DB 0cfh ; 16-bit segment, 4GB limit
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DB 0
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GDT_SIZE equ $ - _NullSeg
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;------------------------------------------------------------------------------
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; IA32_REGISTER_SET *
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; EFIAPI
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; InternalAsmThunk16 (
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; IN IA32_REGISTER_SET *RegisterSet,
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; IN OUT VOID *Transition
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(InternalAsmThunk16)
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ASM_PFX(InternalAsmThunk16):
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BITS 64
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push rbp
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push rbx
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push rsi
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push rdi
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mov ebx, ds
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push rbx ; Save ds segment register on the stack
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mov ebx, es
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push rbx ; Save es segment register on the stack
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mov ebx, ss
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push rbx ; Save ss segment register on the stack
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push fs
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push gs
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mov rsi, rcx
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movzx r8d, word [rsi + IA32_REGS._SS]
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mov edi, [rsi + IA32_REGS._ESP]
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lea rdi, [edi - (IA32_REGS.size + 4)]
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imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16
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mov ebx, edi ; ebx <- stack for 16-bit code
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push IA32_REGS.size / 4
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add edi, eax ; edi <- linear address of 16-bit stack
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pop rcx
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rep movsd ; copy RegSet
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lea ecx, [rdx + (_BackFromUserCode.SavedCr4End - ASM_PFX(m16Start))]
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mov eax, edx ; eax <- transition code address
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and edx, 0fh
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shl eax, 12 ; segment address in high order 16 bits
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lea ax, [rdx + (_BackFromUserCode - ASM_PFX(m16Start))] ; offset address
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stosd ; [edi] <- return address of user code
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sgdt [rsp + 60h] ; save GDT stack in argument space
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movzx r10, word [rsp + 60h] ; r10 <- GDT limit
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lea r11, [rcx + (ASM_PFX(InternalAsmThunk16) - _BackFromUserCode.SavedCr4End) + 0xf]
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and r11, ~0xf ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer
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mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End)], r10w ; save the limit of shadowed GDT table
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mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End) + 2], r11 ; save the base address of shadowed GDT table
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mov rsi, [rsp + 62h] ; rsi <- the original GDT base address
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xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table
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inc rcx ; rcx <- the size of memory to copy
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xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table
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rep movsb ; perform memory copy to shadow GDT table
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mov rcx, r10 ; restore the orignal rcx before memory copy
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mov rdi, r11 ; restore the original rdi before memory copy
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sidt [rsp + 50h] ; save IDT stack in argument space
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mov rax, cr0
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mov [rcx + (_BackFromUserCode.SavedCr0End - 4 - _BackFromUserCode.SavedCr4End)], eax
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and eax, 7ffffffeh ; clear PE, PG bits
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mov rbp, cr4
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mov [rcx - 4], ebp ; save CR4 in _BackFromUserCode.SavedCr4End - 4
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and ebp, ~30h ; clear PAE, PSE bits
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mov esi, r8d ; esi <- 16-bit stack segment
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push DATA32
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pop rdx ; rdx <- 32-bit data segment selector
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lgdt [rcx + (_16Gdtr - _BackFromUserCode.SavedCr4End)]
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mov ss, edx
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pushfq
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lea edx, [rdx + DATA16 - DATA32]
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lea r8, [REL .RetFromRealMode]
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push r8
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mov r8d, cs
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mov [rcx + (_BackFromUserCode.X64JmpEnd - 2 - _BackFromUserCode.SavedCr4End)], r8w
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mov [rcx + (_BackFromUserCode.SavedSpEnd - 8 - _BackFromUserCode.SavedCr4End)], rsp
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jmp dword far [rcx + (_EntryPoint - _BackFromUserCode.SavedCr4End)]
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.RetFromRealMode:
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popfq
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lgdt [rsp + 60h] ; restore protected mode GDTR
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lidt [rsp + 50h] ; restore protected mode IDTR
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lea eax, [rbp - IA32_REGS.size]
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pop gs
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pop fs
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pop rbx
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mov ss, ebx
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pop rbx
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mov es, ebx
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pop rbx
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mov ds, ebx
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pop rdi
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pop rsi
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pop rbx
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pop rbp
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ret
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