d42fdd6f83
* In the Intel whitepaper: --v-- A Tour Beyond BIOS -- Secure SMM Communication https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Security-White-Papers https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_Beyond_BIOS_Secure_SMM_Communication.pdf --^-- bullet#3 in section "Assumption and Recommendation", and bullet#4 in "Call for action", recommend enabling the (adaptive) Memory Type Information feature. * In the Intel whitepaper: --v-- A Tour Beyond BIOS -- Memory Map and Practices in UEFI BIOS https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-white-papers https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_Beyond_BIOS_Memory_Map_And_Practices_in_UEFI_BIOS_V2.pdf --^-- figure#6 describes the Memory Type Information feature in detail; namely as a feedback loop between the Platform PEIM, the DXE IPL PEIM, the DXE Core, and BDS. Implement the missing PlatformPei functionality in OvmfPkg, for fulfilling the Secure SMM Communication recommendation. In the longer term, OVMF should install the WSMT ACPI table, and this patch contributes to that. Notes: - the step in figure#6 where the UEFI variable is copied into the HOB is covered by the DXE IPL PEIM, in the DxeLoadCore() function, - "PcdResetOnMemoryTypeInformationChange" must be reverted to the DEC default TRUE value, because both whitepapers indicate that BDS needs to reset the system if the Memory Type Information changes. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=386 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200310222739.26717-6-lersek@redhat.com> Acked-by: Leif Lindholm <leif@nuviainc.com>
137 lines
2.0 KiB
C
137 lines
2.0 KiB
C
/** @file
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Platform PEI module include file.
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PLATFORM_PEI_H_INCLUDED_
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#define _PLATFORM_PEI_H_INCLUDED_
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#include <IndustryStandard/E820.h>
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VOID
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AddIoMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddIoMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize
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);
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VOID
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AddMemoryRangeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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EFI_PHYSICAL_ADDRESS MemoryLimit
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);
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VOID
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AddReservedMemoryBaseSizeHob (
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EFI_PHYSICAL_ADDRESS MemoryBase,
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UINT64 MemorySize,
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BOOLEAN Cacheable
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);
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VOID
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AddressWidthInitialization (
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VOID
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);
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VOID
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Q35TsegMbytesInitialization (
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VOID
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);
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VOID
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Q35SmramAtDefaultSmbaseInitialization (
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VOID
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);
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EFI_STATUS
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PublishPeiMemory (
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VOID
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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);
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VOID
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QemuUc32BaseInitialization (
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VOID
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);
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VOID
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InitializeRamRegions (
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VOID
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);
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EFI_STATUS
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PeiFvInitialization (
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VOID
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);
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VOID
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MemTypeInfoInitialization (
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VOID
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);
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VOID
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InstallFeatureControlCallback (
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VOID
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);
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VOID
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InstallClearCacheCallback (
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VOID
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);
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EFI_STATUS
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InitializeXen (
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VOID
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);
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BOOLEAN
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XenDetect (
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VOID
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);
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VOID
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AmdSevInitialize (
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VOID
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);
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extern BOOLEAN mXen;
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VOID
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XenPublishRamRegions (
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VOID
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);
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extern EFI_BOOT_MODE mBootMode;
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extern BOOLEAN mS3Supported;
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extern UINT8 mPhysMemAddressWidth;
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extern UINT32 mMaxCpuCount;
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extern UINT16 mHostBridgeDevId;
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extern BOOLEAN mQ35SmramAtDefaultSmbase;
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extern UINT32 mQemuUc32Base;
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#endif // _PLATFORM_PEI_H_INCLUDED_
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