9378310dd8
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2340
Now that an XCODE5 specific CpuExceptionHandlerLib library is in place,
revert the changes made to the ExceptionHandlerAsm.nasm in commit
2db0ccc2d7 ("UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool
chain") so that binary patching of flash code is not performed.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Liming Gao <liming.gao@intel.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <810f67d8604c054c09d17a22f0bcfaeb41ee8e3b.1588856809.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
384 lines
10 KiB
NASM
384 lines
10 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; ExceptionHandlerAsm.Asm
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;
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; Abstract:
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;
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; x64 CPU Exception Handler
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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;
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; CommonExceptionHandler()
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;
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extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions
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extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag
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extern ASM_PFX(CommonExceptionHandler)
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SECTION .data
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DEFAULT REL
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SECTION .text
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ALIGN 8
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AsmIdtVectorBegin:
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%rep 32
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db 0x6a ; push #VectorNum
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db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
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push rax
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mov rax, ASM_PFX(CommonInterruptEntry)
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jmp rax
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%endrep
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AsmIdtVectorEnd:
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HookAfterStubHeaderBegin:
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db 0x6a ; push
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@VectorNum:
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db 0 ; 0 will be fixed
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push rax
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mov rax, HookAfterStubHeaderEnd
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jmp rax
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HookAfterStubHeaderEnd:
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mov rax, rsp
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and sp, 0xfff0 ; make sure 16-byte aligned for exception context
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sub rsp, 0x18 ; reserve room for filling exception data later
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push rcx
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mov rcx, [rax + 8]
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bt [ASM_PFX(mErrorCodeFlag)], ecx
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jnc .0
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push qword [rsp] ; push additional rcx to make stack alignment
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.0:
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xchg rcx, [rsp] ; restore rcx, save Exception Number in stack
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push qword [rax] ; push rax into stack to keep code consistence
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;---------------------------------------;
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; CommonInterruptEntry ;
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;---------------------------------------;
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; The follow algorithm is used for the common interrupt routine.
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; Entry from each interrupt with a push eax and eax=interrupt number
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; Stack frame would be as follows as specified in IA32 manuals:
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;
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; +---------------------+ <-- 16-byte aligned ensured by processor
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; + Old SS +
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; +---------------------+
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; + Old RSP +
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; +---------------------+
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; + RFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + RIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + Vector Number +
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; +---------------------+
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; + RBP +
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; +---------------------+ <-- RBP, 16-byte aligned
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; The follow algorithm is used for the common interrupt routine.
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global ASM_PFX(CommonInterruptEntry)
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ASM_PFX(CommonInterruptEntry):
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cli
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pop rax
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;
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; All interrupt handlers are invoked through interrupt gates, so
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; IF flag automatically cleared at the entry point
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;
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xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx
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and rcx, 0xFF
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cmp ecx, 32 ; Intel reserved vector for exceptions?
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jae NoErrorCode
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bt [ASM_PFX(mErrorCodeFlag)], ecx
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jc HasErrorCode
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NoErrorCode:
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;
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; Push a dummy error code on the stack
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; to maintain coherent stack map
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;
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push qword [rsp]
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mov qword [rsp + 8], 0
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HasErrorCode:
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push rbp
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mov rbp, rsp
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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;
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; Stack:
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; +---------------------+ <-- 16-byte aligned ensured by processor
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; + Old SS +
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; +---------------------+
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; + Old RSP +
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; +---------------------+
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; + RFlags +
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; +---------------------+
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; + CS +
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; +---------------------+
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; + RIP +
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; +---------------------+
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; + Error Code +
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; +---------------------+
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; + RCX / Vector Number +
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; +---------------------+
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; + RBP +
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; +---------------------+ <-- RBP, 16-byte aligned
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;
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;
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; Since here the stack pointer is 16-byte aligned, so
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; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
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; is 16-byte aligned
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;
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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push r15
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push r14
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push r13
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push r12
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push r11
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push r10
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push r9
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push r8
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push rax
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push qword [rbp + 8] ; RCX
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push rdx
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push rbx
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push qword [rbp + 48] ; RSP
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push qword [rbp] ; RBP
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push rsi
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push rdi
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
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movzx rax, word [rbp + 56]
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push rax ; for ss
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movzx rax, word [rbp + 32]
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push rax ; for cs
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mov rax, ds
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push rax
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mov rax, es
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push rax
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mov rax, fs
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push rax
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mov rax, gs
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push rax
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mov [rbp + 8], rcx ; save vector number
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;; UINT64 Rip;
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push qword [rbp + 24]
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;; UINT64 Gdtr[2], Idtr[2];
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xor rax, rax
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push rax
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push rax
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sidt [rsp]
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mov bx, word [rsp]
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mov rax, qword [rsp + 2]
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mov qword [rsp], rax
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mov word [rsp + 8], bx
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xor rax, rax
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push rax
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push rax
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sgdt [rsp]
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mov bx, word [rsp]
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mov rax, qword [rsp + 2]
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mov qword [rsp], rax
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mov word [rsp + 8], bx
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;; UINT64 Ldtr, Tr;
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xor rax, rax
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str ax
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push rax
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sldt ax
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push rax
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;; UINT64 RFlags;
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push qword [rbp + 40]
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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mov rax, cr8
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push rax
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mov rax, cr4
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or rax, 0x208
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mov cr4, rax
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push rax
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mov rax, cr3
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push rax
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mov rax, cr2
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push rax
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xor rax, rax
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push rax
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mov rax, cr0
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push rax
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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mov rax, dr7
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push rax
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mov rax, dr6
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push rax
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mov rax, dr3
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push rax
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mov rax, dr2
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push rax
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mov rax, dr1
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push rax
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mov rax, dr0
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push rax
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;; FX_SAVE_STATE_X64 FxSaveState;
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sub rsp, 512
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mov rdi, rsp
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db 0xf, 0xae, 0x7 ;fxsave [rdi]
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;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
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cld
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;; UINT32 ExceptionData;
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push qword [rbp + 16]
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;; Prepare parameter and call
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mov rcx, [rbp + 8]
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mov rdx, rsp
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;
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; Per X64 calling convention, allocate maximum parameter stack space
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; and make sure RSP is 16-byte aligned
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;
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sub rsp, 4 * 8 + 8
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mov rax, ASM_PFX(CommonExceptionHandler)
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call rax
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add rsp, 4 * 8 + 8
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cli
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;; UINT64 ExceptionData;
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add rsp, 8
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;; FX_SAVE_STATE_X64 FxSaveState;
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mov rsi, rsp
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db 0xf, 0xae, 0xE ; fxrstor [rsi]
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add rsp, 512
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;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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;; Skip restoration of DRx registers to support in-circuit emualators
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;; or debuggers set breakpoint in interrupt/exception context
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add rsp, 8 * 6
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;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
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pop rax
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mov cr0, rax
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add rsp, 8 ; not for Cr1
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pop rax
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mov cr2, rax
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pop rax
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mov cr3, rax
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pop rax
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mov cr4, rax
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pop rax
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mov cr8, rax
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;; UINT64 RFlags;
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pop qword [rbp + 40]
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;; UINT64 Ldtr, Tr;
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;; UINT64 Gdtr[2], Idtr[2];
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;; Best not let anyone mess with these particular registers...
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add rsp, 48
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;; UINT64 Rip;
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pop qword [rbp + 24]
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;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
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pop rax
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; mov gs, rax ; not for gs
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pop rax
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; mov fs, rax ; not for fs
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; (X64 will not use fs and gs, so we do not restore it)
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pop rax
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mov es, rax
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pop rax
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mov ds, rax
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pop qword [rbp + 32] ; for cs
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pop qword [rbp + 56] ; for ss
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;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
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;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
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pop rdi
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pop rsi
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add rsp, 8 ; not for rbp
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pop qword [rbp + 48] ; for rsp
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pop rbx
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pop rdx
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pop rcx
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pop rax
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pop r8
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pop r9
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pop r10
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pop r11
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pop r12
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pop r13
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pop r14
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pop r15
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mov rsp, rbp
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pop rbp
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add rsp, 16
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cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler
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jz DoReturn
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cmp qword [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag
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jz ErrorCode
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jmp qword [rsp - 32]
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ErrorCode:
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sub rsp, 8
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jmp qword [rsp - 24]
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DoReturn:
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cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET
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jz DoIret
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push rax
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mov rax, rsp ; save old RSP to rax
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mov rsp, [rsp + 0x20]
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push qword [rax + 0x10] ; save CS in new location
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push qword [rax + 0x8] ; save EIP in new location
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push qword [rax + 0x18] ; save EFLAGS in new location
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mov rax, [rax] ; restore rax
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popfq ; restore EFLAGS
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DB 0x48 ; prefix to composite "retq" with next "retf"
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retf ; far return
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DoIret:
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iretq
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;-------------------------------------------------------------------------------------
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; GetTemplateAddressMap (&AddressMap);
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;-------------------------------------------------------------------------------------
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; comments here for definition of address map
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global ASM_PFX(AsmGetTemplateAddressMap)
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ASM_PFX(AsmGetTemplateAddressMap):
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mov rax, AsmIdtVectorBegin
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mov qword [rcx], rax
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mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
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mov rax, HookAfterStubHeaderBegin
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mov qword [rcx + 0x10], rax
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ret
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;-------------------------------------------------------------------------------------
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; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmVectorNumFixup)
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ASM_PFX(AsmVectorNumFixup):
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mov rax, rdx
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mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al
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ret
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